{"created":"2025-01-19T01:28:01.917339+00:00","updated":"2025-01-19T11:40:43.762416+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228899","sets":["1164:2036:11089:11372"]},"path":["11372"],"owner":"44499","recid":"228899","title":["メモリズムパターンマッチングアクセラレータのFPGA実装と性能評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-10"},"_buckets":{"deposit":"bcefef1d-0f16-4f62-ab47-b9a25117d104"},"_deposit":{"id":"228899","pid":{"type":"depid","value":"228899","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"メモリズムパターンマッチングアクセラレータのFPGA実装と性能評価","author_link":["614628","614629","614625","614630","614637","614623","614627","614633","614632","614638","614635","614636","614631","614626","614624","614634"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"メモリズムパターンマッチングアクセラレータのFPGA実装と性能評価"},{"subitem_title":"Implementation Evaluation of a Memorism Pattern Matching Accelerator on FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高信頼LSI設計と評価","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"株式会社エイ・オー・テクノロジーズ"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Engineering, Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Engineering, Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Engineering, Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Engineering, Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Engineering, Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Engineering, Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Engineering, Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Advanced Original Technologies Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228899/files/IPSJ-SLDM23204032.pdf","label":"IPSJ-SLDM23204032.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23204032.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"2c351353-536d-4465-8b8f-3619af70683f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"本田, 志遠"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"西川, 竜矢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"周, 細紅"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"王, 森レイ"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"甲斐, 博"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"樋上, 善信"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高橋, 寛"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"井上, 克己"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shion, Honda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tatsuya, Nishikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Xihong, Zhou","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Senling, Wang","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroshi, Kai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshinobu, Higami","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroshi, Takahashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Katsumi, Inoue","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"画像処理と人工知能技術の急速な進展に伴い,膨大な画像データを高速かつ低消費電力で処理できる計算アーキテクチャが求められている.近年,データを格納する記憶素子の近傍に演算素子を配置するインメモリコンピューティング技術が注目を集めている.SOP (Set Operating Processor) は,演算機能付き記憶素子の行列化による並列演算を行う新型パターンマッチングアクセラレータである. 本研究では,SOP の有用性を評価することを目的として,FPGA に SOP を実装し,必要なリソースに関して実装面積評価およびパターンマッチング処理時間の評価を行った.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"With the rapid advancement of image processing and artificial intelligence technologies, there is a demand for computational architectures that can process vast image data in efficient and with low power consumption. In recent years, in- memory computing technology, which places computational elements near the memory elements storing the data, has been gaining attention. SOP (Set Operating Processor) is a new pattern matching accelerator that performs parallel computations by matrixing memory elements with computational functions. In this study, we implemented SOP on FPGA to evaluate its utility, and assessed the implementation area in terms of required resources and the pattern matching processing time.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術(SLDM)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"32","bibliographicVolumeNumber":"2023-SLDM-204"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":228899,"links":{}}