{"created":"2025-01-19T01:28:01.802721+00:00","updated":"2025-01-19T11:40:45.928836+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228897","sets":["1164:2036:11089:11372"]},"path":["11372"],"owner":"44499","recid":"228897","title":["WGAN-GP based AI accelerator fault detection and fault classification analysis"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-10"},"_buckets":{"deposit":"cc09773d-e55e-4184-8b91-1cdb10d6f3c0"},"_deposit":{"id":"228897","pid":{"type":"depid","value":"228897","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"WGAN-GP based AI accelerator fault detection and fault classification analysis","author_link":["614613","614611","614612","614614"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"WGAN-GP based AI accelerator fault detection and fault classification analysis"},{"subitem_title":"WGAN-GP based AI accelerator fault detection and fault classification analysis","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高信頼LSI設計と評価","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Engineering, Chiba University"},{"subitem_text_value":"Graduate School of Science and Engineering, Chiba University"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Engineering, Chiba University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Engineering, Chiba University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228897/files/IPSJ-SLDM23204030.pdf","label":"IPSJ-SLDM23204030.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23204030.pdf","filesize":[{"value":"1.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"dd541a8a-010b-4ba3-9e68-6201b5d926da","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shuming, Xu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazuteru, Namba"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shuming, Xu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazuteru, Namba","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"During the manufacturing phase of artificial intelligence (AI) chips, certain manufacturing faults bear profound significance due to their substantial impact on the precision of executed artificial intelligence wo rkloads. Detecting these critical functional faults necessitates the utilization of automatic test pattern generation (ATPG) tools, commonly employed to supply the requisite test patterns. However, such an approach entails notable costs and can potentially engender production losses. In this paper, we analyze the fault detection capacity predicated upon the criticality of chip functionality. Furthermore, we embark upon the task of categorizing faults within AI accelerators as either critical or benign. To this end, we present a machine learning architecture tailored to achieve fault detection in AI accelerators based on systolic arrays. Notably, we introduce an optimized generative adversarial neural network (GAN) WGAN-GP to ameliorate the misclassification challenges inherent to the designed detection architecture. Our results show that our method can identify faults with fixed accuracy and accurately classify them, thereby reducing production losses.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"During the manufacturing phase of artificial intelligence (AI) chips, certain manufacturing faults bear profound significance due to their substantial impact on the precision of executed artificial intelligence wo rkloads. Detecting these critical functional faults necessitates the utilization of automatic test pattern generation (ATPG) tools, commonly employed to supply the requisite test patterns. However, such an approach entails notable costs and can potentially engender production losses. In this paper, we analyze the fault detection capacity predicated upon the criticality of chip functionality. Furthermore, we embark upon the task of categorizing faults within AI accelerators as either critical or benign. To this end, we present a machine learning architecture tailored to achieve fault detection in AI accelerators based on systolic arrays. Notably, we introduce an optimized generative adversarial neural network (GAN) WGAN-GP to ameliorate the misclassification challenges inherent to the designed detection architecture. Our results show that our method can identify faults with fixed accuracy and accurately classify them, thereby reducing production losses.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"30","bibliographicVolumeNumber":"2023-SLDM-204"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":228897,"links":{}}