WGAN-GP based AI accelerator fault detection and fault classification analysis

• Item type: SIG Technical Reports(1)
• 公開日: 2023-11-10
• タイトル: WGAN-GP based AI accelerator fault detection and fault classification analysis
• タイトル / 言語: en
• タイトル: WGAN-GP based AI accelerator fault detection and fault classification analysis
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 高信頼LSI設計と評価
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Science and Engineering, Chiba University
• 著者所属: Graduate School of Science and Engineering, Chiba University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Chiba University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Chiba University
• 著者名: Shuming, Xu; Kazuteru, Namba
• 著者名(英): Shuming, Xu; Kazuteru, Namba
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: During the manufacturing phase of artificial intelligence (AI) chips, certain manufacturing faults bear profound significance due to their substantial impact on the precision of executed artificial intelligence wo rkloads. Detecting these critical functional faults necessitates the utilization of automatic test pattern generation (ATPG) tools, commonly employed to supply the requisite test patterns. However, such an approach entails notable costs and can potentially engender production losses. In this paper, we analyze the fault detection capacity predicated upon the criticality of chip functionality. Furthermore, we embark upon the task of categorizing faults within AI accelerators as either critical or benign. To this end, we present a machine learning architecture tailored to achieve fault detection in AI accelerators based on systolic arrays. Notably, we introduce an optimized generative adversarial neural network (GAN) WGAN-GP to ameliorate the misclassification challenges inherent to the designed detection architecture. Our results show that our method can identify faults with fixed accuracy and accurately classify them, thereby reducing production losses.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: During the manufacturing phase of artificial intelligence (AI) chips, certain manufacturing faults bear profound significance due to their substantial impact on the precision of executed artificial intelligence wo rkloads. Detecting these critical functional faults necessitates the utilization of automatic test pattern generation (ATPG) tools, commonly employed to supply the requisite test patterns. However, such an approach entails notable costs and can potentially engender production losses. In this paper, we analyze the fault detection capacity predicated upon the criticality of chip functionality. Furthermore, we embark upon the task of categorizing faults within AI accelerators as either critical or benign. To this end, we present a machine learning architecture tailored to achieve fault detection in AI accelerators based on systolic arrays. Notably, we introduce an optimized generative adversarial neural network (GAN) WGAN-GP to ameliorate the misclassification challenges inherent to the designed detection architecture. Our results show that our method can identify faults with fixed accuracy and accurately classify them, thereby reducing production losses.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11451459
• 書誌情報: 研究報告システムとLSIの設計技術（SLDM）; 巻 2023-SLDM-204, 号 30, p. 1-6, 発行日 2023-11-10
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-8639
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会