{"id":228889,"updated":"2025-01-19T11:40:56.247440+00:00","links":{},"created":"2025-01-19T01:28:01.343271+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228889","sets":["1164:2036:11089:11372"]},"path":["11372"],"owner":"44499","recid":"228889","title":["メモリ型論理再構成装置における ニューラルネットワークの実装について"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-10"},"_buckets":{"deposit":"477e4356-dc54-4765-ae2f-2ee219f0cd45"},"_deposit":{"id":"228889","pid":{"type":"depid","value":"228889","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"メモリ型論理再構成装置における ニューラルネットワークの実装について","author_link":["614564","614558","614561","614557","614559","614556","614563","614562","614555","614560","614553","614554"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"メモリ型論理再構成装置における ニューラルネットワークの実装について"},{"subitem_title":"Implementation of Neural Networks in Memory-based Reconfigurable Processor","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ハードウェアセキュリティ，VLSI実装技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"},{"subitem_text_value":"愛媛大学大学院理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Ehime University","subitem_text_language":"en"},{"subitem_text_value":"Ehime University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228889/files/IPSJ-SLDM23204022.pdf","label":"IPSJ-SLDM23204022.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23204022.pdf","filesize":[{"value":"2.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"340107c5-7e03-4e6b-850c-dfe899227dfe","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"笹川, 健太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"西川, 竜矢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"周, 細紅"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"王, 森レイ"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"甲斐, 博"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高橋, 寛"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kenta, Sasagawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tatsuya, Nishikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Xihong, Zhou","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Senling, Wang","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroshi, Kai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroshi, Takahashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年の IoT 技術の発展によってネットワークの末端のデータが発生する箇所の機器において知的処理を実装することが求められており，再構成可能デバイスが注目されている．再構成可能デバイスの一つである MRP (Memory-based Reconfigurable Processor) はメモリを主体とした再構成可能デバイスで，FPGA などの他の再構成可能デバイスと比較して処理速度やコスト面で優れており，知的処理の根幹となるニューラルネットワーク（NN）実装も可能であるが，特殊な構造を持つために高信頼な NN を実装する手法は現在確立されていない．そこで，本研究では MRP の構造に適応した NN 構造である MNN の提案とその精度評価を行った．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"With the development of recent IoT technologies，there is a demand to implement intelligent processing in devices where data is generated at the edge of the network，and reconfigurable devices are drawing attention. MRP，one of the reconfigurable devices，is a memory-centric reconfigurable device. Compared to other reconfigurable devices such as FPGA， it excels in processing speed and cost-effectiveness. While it is possible to implement Neural Networks (NN)，which are the core of intelligent processing，the method for implementing a highly reliable NN is not yet established due to its unique structure. Therefore，in this study，we proposed an NN structure adapted to the MRP structure，called MNN，and evaluated its accuracy. ","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"5","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"22","bibliographicVolumeNumber":"2023-SLDM-204"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}