{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228846","sets":["1164:2036:11089:11357"]},"path":["11357"],"owner":"44499","recid":"228846","title":["量子コンピュータ制御装置のASIC化に向けた10GbpsクラスDeserializerの開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-10-31"},"_buckets":{"deposit":"53ee0365-bf33-4c12-997a-312f9b64388f"},"_deposit":{"id":"228846","pid":{"type":"depid","value":"228846","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"量子コンピュータ制御装置のASIC化に向けた10GbpsクラスDeserializerの開発","author_link":["614300","614299","614302","614301"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"量子コンピュータ制御装置のASIC化に向けた10GbpsクラスDeserializerの開発"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ポスター","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-10-31","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都工芸繊維大学"},{"subitem_text_value":"京都工芸繊維大学"},{"subitem_text_value":"明治大学"},{"subitem_text_value":"キュエル株式会社"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyoto Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Kyoto Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Meiji University","subitem_text_language":"en"},{"subitem_text_value":"QuEL, Inc.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228846/files/IPSJ-SLDM23203011.pdf","label":"IPSJ-SLDM23203011.pdf"},"date":[{"dateType":"Available","dateValue":"2025-10-31"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23203011.pdf","filesize":[{"value":"241.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d29ff1e6-ada7-4181-9562-fb009e162438","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小山, 雄輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小林, 和淑"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"今川, 隆司"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"三好, 健文"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"量子コンピュータ制御装置の Application specific integrated circuit (ASIC) 化において，量子ビットを読み出した Analog-to-Digital Converter (ADC) 信号の受信が課題となっている．既存のシステムでは ADC 信号のデータレートは 13.3Gbps であり，高データレートの伝送規格である JESD204C を利用することにより省配線での伝送を可能としている．しかし，ASIC 化の研究の過程で数 GHz クラスの信号を取り扱うことや，高機能なレシーバの実装は負担が大きい．そこで，配線数は増加するものの数百 MHz クラスの信号である Low voltage differential signaling (LVDS) 規格を用いることにより，高速な信号伝送を手軽に実装することを考える．LVDS の構成は，100MHz の送信クロックによる 700Mbps 信号線 19 レーンを想定する．この構成をもとに，ASIC 側の LVDS 受信回路のシフトレジスタと取り出し用のタイミング生成回路を VHDL 言語にて記述した．今後は，受信に伴うスキュー調整が必要なことから信号のタイミングを検出する回路の記述を行い，22nm プロセスにて ASIC に実装する．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"3","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-10-31","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"11","bibliographicVolumeNumber":"2023-SLDM-203"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":228846,"updated":"2025-01-19T11:41:51.998825+00:00","links":{},"created":"2025-01-19T01:27:58.866449+00:00"}