{"id":227817,"updated":"2025-01-19T12:03:12.219524+00:00","links":{},"created":"2025-01-19T01:27:04.152874+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00227817","sets":["1164:2240:11176:11333"]},"path":["11333"],"owner":"44499","recid":"227817","title":["次世代計算基盤に向けたノードアーキテクチャの初期検討結果と課題分析"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-09-19"},"_buckets":{"deposit":"baf51237-f979-4309-bf9e-e4d4d8bfcd25"},"_deposit":{"id":"227817","pid":{"type":"depid","value":"227817","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"次世代計算基盤に向けたノードアーキテクチャの初期検討結果と課題分析","author_link":["607395","607392","607397","607393","607390","607389","607391","607394","607396","607398","607399","607388"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"次世代計算基盤に向けたノードアーキテクチャの初期検討結果と課題分析"},{"subitem_title":"Initial Study Results and Issue Analysis of Node Architecture for the Next-Generation Computing Infrastructure","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"次世代計算基盤","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-09-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Fujitsu Limited","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Limited","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Limited","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Limited","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Limited","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Limited","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/227817/files/IPSJ-HPC23191005.pdf","label":"IPSJ-HPC23191005.pdf"},"date":[{"dateType":"Available","dateValue":"2025-09-19"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC23191005.pdf","filesize":[{"value":"508.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"dbcf4947-79bd-45ad-8bdd-7d5c62c35d6b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"安島, 雄一郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"本車田, 強"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"秋谷, 定則"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小田嶋, 哲哉"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉川, 隆英"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"水谷, 康志"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuichiro, Ajima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsuyoshi, Motokurumada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Sadanori, Akiya","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tetsuya, Odajima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takahide, Yoshikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yasushi, Mizutani","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8841","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ポスト「富岳」時代の次世代計算基盤に向けた文部科学省の調査研究が 2022 年度より開始されている.我々は理化学研究所のシステム調査研究におけるアーキテクチャ調査研究サブグループ 2 として調査研究を実施している.2022 年度の調査研究では技術動向調査により構築可能なアーキテクチャの探索空間を確立した.技術動向調査では構成要素毎に 2028 年頃の製造開始を想定して性能やコストをモデル化し,構成要素の組合せを変えた様々なノードアーキテクチャの性能,製造コスト,設計コストの予測を可能にした.第 189 回 HPC 研究会ではプロセッサおよびメモリの調査研究結果を使用し,チップレット技術を使用して設計コストを下げるプロセッサアーキテクチャと高帯域メモリの組合せが性能とコストのバランスが良いことを示した.このノードアーキテクチャでは演算性能を強化するためにアクセラレータが必要になる.しかし第 189 回 HPC 研究会の発表では,まだアクセラレータのモデル化の初期検討が完了していなかったため,アクセラレータを組み込んだ評価を実施できなかった.本稿ではアクセラレータの調査研究結果を使用し,演算密度の高い Systolic Array 型および柔軟性の高いデータフロー型のアクセラレータを組み込んだノードアーキテクチャの初期検討を行う.また検討結果を分析し,今後の課題について述べる.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The Ministry of Education, Culture, Sports, Science and Technology (MEXT) has started the next-generation computing infrastructure for the post-Fugaku era project in FY2022. We are conducting the research as subgroup 2 of the architecture research group of the RIKEN system feasibility study team and have established a search space of possible architectures through a technology trend survey in FY2022. In the technology trend survey, we modeled the performance and cost of each component, assuming the start of manufacturing around 2028 to predict the performance, manufacturing cost, and design cost of various node architectures with different combinations of components. At the 189th IPSJ SIGHPC Workshop, we used the results of the processor and memory studies to show that a combination of processor architecture that uses chiplet technology to lower design costs and high-bandwidth memory provides a good balance between performance and cost. This node architecture requires accelerators to enhance computing performance. However, at the time of the 189th Workshop, the initial study of accelerator modeling had not yet been completed, so an evaluation incorporating an accelerator could not be performed. In this paper, we use the results of our accelerator research to conduct an initial study of node architectures that incorporate a systolic array type accelerator with high compute density and a dataflow type accelerator with high flexibility. We also analyze the results and discuss future issues.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング(HPC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-09-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"2023-HPC-191"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}