{"updated":"2025-01-19T12:11:24.813858+00:00","links":{},"id":227387,"created":"2025-01-19T01:26:39.268044+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00227387","sets":["6164:6165:7651:11316"]},"path":["11316"],"owner":"44499","recid":"227387","title":["バンドギャップ基準電圧回路におけるバラツキ抑制を考慮した設計アプローチ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-08-23"},"_buckets":{"deposit":"c21505dc-7e67-4eac-812f-f6dbe06efaf1"},"_deposit":{"id":"227387","pid":{"type":"depid","value":"227387","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"バンドギャップ基準電圧回路におけるバラツキ抑制を考慮した設計アプローチ","author_link":["605655","605654","605652","605653"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"バンドギャップ基準電圧回路におけるバラツキ抑制を考慮した設計アプローチ"},{"subitem_title":"A Design Approach of BGR Circuit With a Circuit to Suppress Variation","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ポスター","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2023-08-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"高知工科大学"},{"subitem_text_value":"高知工科大学"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kochi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Kochi University of Technology","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/227387/files/IPSJ-DAS2023022.pdf","label":"IPSJ-DAS2023022.pdf"},"date":[{"dateType":"Available","dateValue":"2025-08-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2023022.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"fdbde05a-dbe4-48e4-b657-e8ae3231152a","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"林, 竜史"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"橘, 昌良"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryuji, Hayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masayoshi, Tachibana","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では，BGR (Band-Gap Reference) 回路を対象とし出力電圧のバラツキ抑制回路の提案及び試作を行った．試作した回路は PMOS で構成したキャリブレーション回路を搭載し，出力電圧を調整することが可能である．これによりトリミング装置を必要とせず，出力電圧のバラツキを抑制することが可能になる．またバラツキの要因の一つであるオフセット電圧を考慮した設計も行った．本論文で設計した BGR 回路は電源電圧 1.8V において出力電圧は 1.0V である．結果として，キャリブレーション回路を搭載することで，電源電圧 1.8V における出力電圧のバラツキを 7% 以下に抑制することが可能となった．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This study proposes and fabricates a circuit for suppressing output voltage variations in a BGR (Band-Gap Reference) circuit. The prototype circuit is equipped with a calibration circuit composed of PMOS, and the output voltage can be adjusted. This eliminates the need for trimming equipment and suppresses output voltage variations. The design also took into account offset voltage, which is one of the factors causing variation. In this paper, the target value of the BGR circuit has an output voltage of 1.0V at a supply voltage of 1.8V. As a result, the output voltage variation at a supply voltage of 1.8V can be suppressed to less than 7% by adding a calibration circuit.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"140","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2023論文集"}],"bibliographicPageStart":"135","bibliographicIssueDates":{"bibliographicIssueDate":"2023-08-23","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2023"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}