{"id":227386,"updated":"2025-01-19T12:11:25.894385+00:00","links":{},"created":"2025-01-19T01:26:39.211152+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00227386","sets":["6164:6165:7651:11316"]},"path":["11316"],"owner":"44499","recid":"227386","title":["Energy-Efficient and Real-Time FPGA-based YOLOv6 Accelerator for Object Detection"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-08-23"},"_buckets":{"deposit":"69d52edc-eae4-4dc7-8920-b8d35c67e894"},"_deposit":{"id":"227386","pid":{"type":"depid","value":"227386","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Energy-Efficient and Real-Time FPGA-based YOLOv6 Accelerator for Object Detection","author_link":["605645","605646","605651","605649","605647","605642","605650","605643","605644","605648"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Energy-Efficient and Real-Time FPGA-based YOLOv6 Accelerator for Object Detection"},{"subitem_title":"Energy-Efficient and Real-Time FPGA-based YOLOv6 Accelerator for Object Detection","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ポスター","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2023-08-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Waseda University"},{"subitem_text_value":"Waseda University"},{"subitem_text_value":"Waseda University"},{"subitem_text_value":"Waseda University"},{"subitem_text_value":"Waseda University"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/227386/files/IPSJ-DAS2023021.pdf","label":"IPSJ-DAS2023021.pdf"},"date":[{"dateType":"Available","dateValue":"2025-08-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2023021.pdf","filesize":[{"value":"4.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"4be56eee-d60d-454f-b0e8-41f11eadb07d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Xingan, Sha"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Zeqiu, Liu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuejie, Meng"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masao, Yanagisawa"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Youhua, Shi"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Xingan, Sha","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Zeqiu, Liu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuejie, Meng","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Youhua, Shi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Convolutional neural networks (CNNs) are widely utilized in object detection due to their exceptional accuracy. However, it is challenging to deploy them in the power-constrained and resource-constrained edge applications for their large computational workload. Among different CNN algorithms, the YOLO [1] series offers a superior balance between speed and accuracy. Furthermore, field-programmable gate arrays (FPGAs) have advantages over Graphics Processing Units (GPUs) and Application-Specific Integrated Circuits (ASICs) in terms of cost, energy efficiency, reconfigurability, and short development cycles. Therefore, this study aims to develop a high-performance and energy-efficient FPGA-based YOLO accelerator, implemented on the VC707 FPGA board. In this paper, the state-ofart YOLOv6 [2] featuring compact and hardware friendly is deployed on FPGA, which achieves 84.9% mean average precision (mAP) in PASCAL VOC2007 dataset far exceeding the accuracy of most existing YOLO accelerators. In addition, the proposed FPGA-based accelerator design adopting the output stationary dataflow and the double buffers scheme with a ping-pong mechanism can eliminate almost all energy-costive and time-consuming DRAM accesses. Experiments show that this hardware design achieves 364.5 frames per second (fps) and 18.46W on Virtex 7 VX485T FPGA under 150 MHz.","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Convolutional neural networks (CNNs) are widely utilized in object detection due to their exceptional accuracy. However, it is challenging to deploy them in the power-constrained and resource-constrained edge applications for their large computational workload. Among different CNN algorithms, the YOLO [1] series offers a superior balance between speed and accuracy. Furthermore, field-programmable gate arrays (FPGAs) have advantages over Graphics Processing Units (GPUs) and Application-Specific Integrated Circuits (ASICs) in terms of cost, energy efficiency, reconfigurability, and short development cycles. Therefore, this study aims to develop a high-performance and energy-efficient FPGA-based YOLO accelerator, implemented on the VC707 FPGA board. In this paper, the state-ofart YOLOv6 [2] featuring compact and hardware friendly is deployed on FPGA, which achieves 84.9% mean average precision (mAP) in PASCAL VOC2007 dataset far exceeding the accuracy of most existing YOLO accelerators. In addition, the proposed FPGA-based accelerator design adopting the output stationary dataflow and the double buffers scheme with a ping-pong mechanism can eliminate almost all energy-costive and time-consuming DRAM accesses. Experiments show that this hardware design achieves 364.5 frames per second (fps) and 18.46W on Virtex 7 VX485T FPGA under 150 MHz.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"134","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2023論文集"}],"bibliographicPageStart":"129","bibliographicIssueDates":{"bibliographicIssueDate":"2023-08-23","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2023"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}