Energy-Efficient and Real-Time FPGA-based YOLOv6 Accelerator for Object Detection

• Item type: Symposium(1)
• 公開日: 2023-08-23
• タイトル: Energy-Efficient and Real-Time FPGA-based YOLOv6 Accelerator for Object Detection
• タイトル / 言語: en
• タイトル: Energy-Efficient and Real-Time FPGA-based YOLOv6 Accelerator for Object Detection
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: ポスター
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_5794
• 資源タイプ: conference paper
• 著者所属: Waseda University
• 著者所属: Waseda University
• 著者所属: Waseda University
• 著者所属: Waseda University
• 著者所属: Waseda University
• 著者所属(英): en
• 著者所属(英): Waseda University
• 著者所属(英): en
• 著者所属(英): Waseda University
• 著者所属(英): en
• 著者所属(英): Waseda University
• 著者所属(英): en
• 著者所属(英): Waseda University
• 著者所属(英): en
• 著者所属(英): Waseda University
• 著者名: Xingan, Sha; Zeqiu, Liu; Yuejie, Meng; Masao, Yanagisawa; Youhua, Shi
• 著者名(英): Xingan, Sha; Zeqiu, Liu; Yuejie, Meng; Masao, Yanagisawa; Youhua, Shi
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Convolutional neural networks (CNNs) are widely utilized in object detection due to their exceptional accuracy. However, it is challenging to deploy them in the power-constrained and resource-constrained edge applications for their large computational workload. Among different CNN algorithms, the YOLO [1] series offers a superior balance between speed and accuracy. Furthermore, field-programmable gate arrays (FPGAs) have advantages over Graphics Processing Units (GPUs) and Application-Specific Integrated Circuits (ASICs) in terms of cost, energy efficiency, reconfigurability, and short development cycles. Therefore, this study aims to develop a high-performance and energy-efficient FPGA-based YOLO accelerator, implemented on the VC707 FPGA board. In this paper, the state-ofart YOLOv6 [2] featuring compact and hardware friendly is deployed on FPGA, which achieves 84.9% mean average precision (mAP) in PASCAL VOC2007 dataset far exceeding the accuracy of most existing YOLO accelerators. In addition, the proposed FPGA-based accelerator design adopting the output stationary dataflow and the double buffers scheme with a ping-pong mechanism can eliminate almost all energy-costive and time-consuming DRAM accesses. Experiments show that this hardware design achieves 364.5 frames per second (fps) and 18.46W on Virtex 7 VX485T FPGA under 150 MHz.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Convolutional neural networks (CNNs) are widely utilized in object detection due to their exceptional accuracy. However, it is challenging to deploy them in the power-constrained and resource-constrained edge applications for their large computational workload. Among different CNN algorithms, the YOLO [1] series offers a superior balance between speed and accuracy. Furthermore, field-programmable gate arrays (FPGAs) have advantages over Graphics Processing Units (GPUs) and Application-Specific Integrated Circuits (ASICs) in terms of cost, energy efficiency, reconfigurability, and short development cycles. Therefore, this study aims to develop a high-performance and energy-efficient FPGA-based YOLO accelerator, implemented on the VC707 FPGA board. In this paper, the state-ofart YOLOv6 [2] featuring compact and hardware friendly is deployed on FPGA, which achieves 84.9% mean average precision (mAP) in PASCAL VOC2007 dataset far exceeding the accuracy of most existing YOLO accelerators. In addition, the proposed FPGA-based accelerator design adopting the output stationary dataflow and the double buffers scheme with a ping-pong mechanism can eliminate almost all energy-costive and time-consuming DRAM accesses. Experiments show that this hardware design achieves 364.5 frames per second (fps) and 18.46W on Virtex 7 VX485T FPGA under 150 MHz.
• 書誌情報: DAシンポジウム2023論文集; 巻 2023, p. 129-134, 発行日 2023-08-23
• 出版者 / 言語: ja
• 出版者: 情報処理学会