@inproceedings{oai:ipsj.ixsq.nii.ac.jp:00227385,
 author = {Zeqiu, Liu and Xingan, Sha and Haoyang, Tao and Masao, Yanagisawa and Youhua, Shi and Zeqiu, Liu and Xingan, Sha and Haoyang, Tao and Masao, Yanagisawa and Youhua, Shi},
 book = {DAシンポジウム2023論文集},
 month = {Aug},
 note = {Object detection has been a consistently popular research area, but achieving higher performance often necessitates complex structures that rely on powerful hardware. However, deploying such high-performance hardware on edge systems is challenging due to its high cost and power consumption. Conversely, simpler structures may lack accuracy, especially when edge hardware requires quantized models, resulting in a significant performance decline. To address these hardware-related challenges, we focus on developing an optimized structure for object detection on edge devices. We examine the dilemma of structure design and the quantization process for object detection, as well as advancements in re-parameterized structures. In order to optimize the model, we modify the original YOLOv6n structure to reduce hardware resource consumption and improve inference speed. We conduct a novel method QARep for re-parameterization, naming the new model QR-YOLOv6n. The results demonstrate that the QR-YOLOv6n retains its quantization-friendly characteristics, with its INT6 version with only 3.1M parameters achieving 81% mAP(mean Average Precision) on Pascal VOC 2007 dataset and 2.74ms latency on customized FPGA, which is acceptable in terms of performance. The evaluation on a customized dataset also reaches a satisfied mAP. With its low latency, high accuracy, and hardware-friendly structure, QR-YOLOv6n presents a potential solution for edge devices, enabling object detection with low power consumption and high accuracy. This research aims to reduce the cost of AI applications and facilitate the widespread deployment of AI in edge systems., Object detection has been a consistently popular research area, but achieving higher performance often necessitates complex structures that rely on powerful hardware. However, deploying such high-performance hardware on edge systems is challenging due to its high cost and power consumption. Conversely, simpler structures may lack accuracy, especially when edge hardware requires quantized models, resulting in a significant performance decline. To address these hardware-related challenges, we focus on developing an optimized structure for object detection on edge devices. We examine the dilemma of structure design and the quantization process for object detection, as well as advancements in re-parameterized structures. In order to optimize the model, we modify the original YOLOv6n structure to reduce hardware resource consumption and improve inference speed. We conduct a novel method QARep for re-parameterization, naming the new model QR-YOLOv6n. The results demonstrate that the QR-YOLOv6n retains its quantization-friendly characteristics, with its INT6 version with only 3.1M parameters achieving 81% mAP(mean Average Precision) on Pascal VOC 2007 dataset and 2.74ms latency on customized FPGA, which is acceptable in terms of performance. The evaluation on a customized dataset also reaches a satisfied mAP. With its low latency, high accuracy, and hardware-friendly structure, QR-YOLOv6n presents a potential solution for edge devices, enabling object detection with low power consumption and high accuracy. This research aims to reduce the cost of AI applications and facilitate the widespread deployment of AI in edge systems.},
 pages = {124--128},
 publisher = {情報処理学会},
 title = {Optimizing Hardware-Friendly Object Detection Network for Edge Devices},
 volume = {2023},
 year = {2023}
}