@inproceedings{oai:ipsj.ixsq.nii.ac.jp:00227369,
 author = {潮田, 裕也 and 金子, 峰雄 and Yuya, Ushioda and Mineo, Kaneko},
 book = {DAシンポジウム2023論文集},
 month = {Aug},
 note = {Two-Level Adiabatic Logic（2LAL） 型断熱論理回路は，断熱論理回路の中でも漸近的断熱性を持ち，優れた消費電力性能が期待される．その一方，断熱論理回路特有の逆計算（消去計算）や各論理ゲートにおける入力信号のタイミング同期化のために多くのバッファ回路が必要となり，その削減が大きな課題となっている．本稿では，「早期消去計算」の導入によるバッファ数削減に関して，論理ゲートのパイプラインステージ割り当てと早期消去計算の挿入位置決定を同時に最適化する整数線形計画法を提案し，ISCAS-85 ベンチマーク回路を用いた合成実験により，従来手法との性能比較を行う．, Two-Level Adiabatic Logic (2LAL) are expected to have asymptotically adiabatic property and excellent power consumption performance among adiabatic logic circuits. On the other hand, many buffer circuits are required for the inverse computation (decompute) peculiar to adiabatic logic circuits and for timing synchronization of input signals at each logic gate, and their reduction is a major issue. In this paper, we propose an integer linear programming method for reducing the number of buffers by introducing an ”early decompute” that simultaneously optimizes the pipeline stage assignment of logic gates and the insertion position of the early decompute, and compare its performance with existing methods through design experiments using the ISCAS-85 benchmark circuit.},
 pages = {15--22},
 publisher = {情報処理学会},
 title = {整数線形計画法による2LAL型断熱論理回路の論理演算パイプライン最適化},
 volume = {2023},
 year = {2023}
}