{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00227194","sets":["934:1119:11299:11300"]},"path":["11300"],"owner":"44499","recid":"227194","title":["Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-07-31"},"_buckets":{"deposit":"6ec42b88-8717-49ff-af8e-b91ed231b99d"},"_deposit":{"id":"227194","pid":{"type":"depid","value":"227194","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers","author_link":["604912","604908","604915","604916","604911","604913","604909","604907","604910","604914"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers"},{"subitem_title":"Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"single-board computer, neural network, dynamic frequency and voltage scaling (DFS/DVFS)","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2023-07-31","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Kyushu University"},{"subitem_text_value":"Kyushu University"},{"subitem_text_value":"Kyushu University"},{"subitem_text_value":"Kyushu University"},{"subitem_text_value":"Kyushu University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Kyushu University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/227194/files/IPSJ-TACS1601004.pdf","label":"IPSJ-TACS1601004.pdf"},"date":[{"dateType":"Available","dateValue":"2025-07-31"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS1601004.pdf","filesize":[{"value":"1.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"c981d075-79a0-4577-9c33-1a7dfe1aec82","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kuan, Yi Ng"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Aalaa, M.A. Babai"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Teruo, Tanimoto"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Satoshi, Kawakami"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Koji, Inoue"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kuan, Yi Ng","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Aalaa, M.A. Babai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Teruo, Tanimoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Satoshi, Kawakami","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Koji, Inoue","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper analyzes the impact of input sparsity and DFS/DVFS configurations for single-board computers on the execution time, power, and energy of each VGG16 layer as the first step towards efficient CNN inference on single-board computers. For this purpose, we first develop a power and execution time measurement environment and perform experiments using Raspberry Pi 4 and NVIDIA Jetson Nano. Our results show that clock frequency strongly correlates with execution time and power. Inversely, input sparsity has a weak correlation with execution time and power. Then, we show that a coarse-grained DVFS model can explain over 96% of the variations in the power of each VGG16 layer even when sets of clock frequency and voltage on the single-board computer are unavailable.\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.31(2023) (online)\n------------------------------","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper analyzes the impact of input sparsity and DFS/DVFS configurations for single-board computers on the execution time, power, and energy of each VGG16 layer as the first step towards efficient CNN inference on single-board computers. For this purpose, we first develop a power and execution time measurement environment and perform experiments using Raspberry Pi 4 and NVIDIA Jetson Nano. Our results show that clock frequency strongly correlates with execution time and power. Inversely, input sparsity has a weak correlation with execution time and power. Then, we show that a coarse-grained DVFS model can explain over 96% of the variations in the power of each VGG16 layer even when sets of clock frequency and voltage on the single-board computer are unavailable.\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.31(2023) (online)\n------------------------------","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム（ACS）"}],"bibliographicIssueDates":{"bibliographicIssueDate":"2023-07-31","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"16"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:26:30.375750+00:00","updated":"2025-01-19T12:14:38.046575+00:00","id":227194}