{"id":226993,"updated":"2025-01-19T12:18:45.747531+00:00","links":{},"created":"2025-01-19T01:26:18.659166+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00226993","sets":["1164:3925:11156:11295"]},"path":["11295"],"owner":"44499","recid":"226993","title":["集約署名方式の署名生成ハードウェアを内蔵するセキュア暗号ユニットSCUとその FPGA実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-07-17"},"_buckets":{"deposit":"c89286bc-a68a-4169-9213-192fe8bfcb33"},"_deposit":{"id":"226993","pid":{"type":"depid","value":"226993","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"集約署名方式の署名生成ハードウェアを内蔵するセキュア暗号ユニットSCUとその FPGA実装","author_link":["603865","603862","603877","603861","603870","603875","603876","603872","603871","603863","603866","603864","603868","603873","603878","603869","603874","603867"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"集約署名方式の署名生成ハードウェアを内蔵するセキュア暗号ユニットSCUとその FPGA実装"},{"subitem_title":"Secure Cryptographic Unit with built-in Signature Generation Hardware for Aggregate Signature Schemes and its FPGA Implementation","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"HWS","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-07-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"株式会社SCU"},{"subitem_text_value":"株式会社SCU"},{"subitem_text_value":"東京大学工学部"},{"subitem_text_value":"横浜国立大学"},{"subitem_text_value":"横浜国立大学"},{"subitem_text_value":"横浜国立大学"},{"subitem_text_value":"東京大学工学部"},{"subitem_text_value":"横浜国立大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"SCU Co., Ltd.","subitem_text_language":"en"},{"subitem_text_value":"SCU Co., Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, the University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Yokohama National Univercity","subitem_text_language":"en"},{"subitem_text_value":"Yokohama National Univercity","subitem_text_language":"en"},{"subitem_text_value":"Yokohama National Univercity","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, the University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Yokohama National Univercity","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/226993/files/IPSJ-CSEC23102056.pdf","label":"IPSJ-CSEC23102056.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-CSEC23102056.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"30"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"64dc469d-3a73-42b1-8c80-c4f2ef71a6af","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐藤, 俊寛"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"川嵜, 将平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"正田, 薫"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"安西, 陸"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"坂本, 純一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉田, 直樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"植村, 泰佳"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"池田, 誠"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松本, 勉"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Toshihiro, Sato","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shohei, Kawasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kaoru, Masada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Riku, Anzai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Junichi, Sakamoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naoki, Yoshida","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yasuyoshi, Uemura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Makoto, Ikeda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsutomu, Matsumoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11235941","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8655","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"セキュア暗号ユニット SCU はハードウェア暗号エンジンとそのアクセス制御機構とから構成され,IoT の末端ノード等を構成するマイクロコントローラやシステム・オン・チップ(SoC)などの半導体チップに搭載可能な信頼の基点である.楕円曲線暗号・共通鍵暗号 AES・ハッシュ関数・乱数生成等のハードウェア実装をアクセス制御付きで提供する SCU を搭載した ASIC チップは既に存在している.本稿では,集約署名方式の署名生成機能を追加した新たな SCU の研究開発と,それを搭載したチップの FPGA 実装につき報告する.またこの SCU 搭載チップを活用した集約署名方式のモデルシステムの構成と評価について報告する.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Secure Cryptographic Unit (SCU) consists of a hardware cryptographic engine and an access control mechanism for the engine, and is a root of trust that can be mounted on semiconductor chips such as microcontrollers and system-on-chips (SoCs) that constitute the end nodes of IoT systems, etc. There already exist ASIC chips equipped with SCU that provides hardware implementation of elliptic curve cryptography, AES, hash function, random number generator, etc. In this paper, we report on an SCU with a new function for generating signatures in the aggregate signature scheme and the FPGA implementation of the chip with this SCU. In addition, we report on the configuration and evaluation of a model system for Aggregate Signature Schemes that utilizes the SCU-equipped chip.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告コンピュータセキュリティ(CSEC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-07-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"56","bibliographicVolumeNumber":"2023-CSEC-102"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}