{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00225471","sets":["1164:2036:11089:11180"]},"path":["11180"],"owner":"44499","recid":"225471","title":["Jupyter Notebookを介したRISC-V SoC向け実機テスト環境の構築"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-03-16"},"_buckets":{"deposit":"4be40a91-0be8-43f7-a198-f9d70dc65f79"},"_deposit":{"id":"225471","pid":{"type":"depid","value":"225471","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Jupyter Notebookを介したRISC-V SoC向け実機テスト環境の構築","author_link":["596649","596646","596645","596648","596647","596650"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Jupyter Notebookを介したRISC-V SoC向け実機テスト環境の構築"},{"subitem_title":"A Chip Testing Methodology for RISC-V SoC Using Jupyter Notebook","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"セキュリティおよびプロセッサシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-03-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院情報理工学系研究科／JSTさきがけ"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"熊本大学大学院先端科学研究部"},{"subitem_text_value":"熊本大学大学院先端科学研究部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo / JST PRESTO","subitem_text_language":"en"},{"subitem_text_value":"Keio Uniersity","subitem_text_language":"en"},{"subitem_text_value":"Keio Uniersity","subitem_text_language":"en"},{"subitem_text_value":"Keio Uniersity","subitem_text_language":"en"},{"subitem_text_value":"Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Kumamoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/225471/files/IPSJ-SLDM23202024.pdf","label":"IPSJ-SLDM23202024.pdf"},"date":[{"dateType":"Available","dateValue":"2025-03-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23202024.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"541813bf-e70b-43a7-bcc6-8a1275b347fe","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小島, 拓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"亀井, 愛佳"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"矢内, 洋祐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"久我, 守弘"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Society5.0 時代で重要視される MEC (Multi-Access Edge Computing) では，エッジデバイスとクラウドサーバの中間にエッジサーバを配置し，データの機密性向上，計算処理や通信の低遅延化が期待されている．こうしたエッジサーバでは，高スループット性，処理時間の予測可能性および低消費電力性が求められており，従来の汎用プロセッサを中心とする汎用サーバに変わり，FPGA などの再構成可能ハードウェアを用いたヘテロジニアスな計算機システムの利用が必要である．SLMLET は RISC-V コアと SLM 再構成ロジックで構成される SoC (Syctem-on-a-Chip) で，こうした用途を想定し開発が進められている．本研究では，昨年テープアウトされた SLMLET を効率的にテストおよび評価するための環境構築を行い，チップの機能検証と動作条件の測定を自動化した．電源電圧や動作周波数，テストベクタなど合計 10000 を超える測定条件に関して，手動の操作を挟むことなく測定することに成功した．評価結果によれば，テープアウトされた SLMLET チップの RISC-V コア部は 120MHz 動作時に 0.56V で動作可能であることがわかった．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-03-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"24","bibliographicVolumeNumber":"2023-SLDM-202"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:24:58.837885+00:00","updated":"2025-01-19T12:47:59.248159+00:00","id":225471}