{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00223481","sets":["1164:2036:11089:11090"]},"path":["11090"],"owner":"44499","recid":"223481","title":["マルチFPGA上でのVision Transformerの並列実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-01-16"},"_buckets":{"deposit":"da0ff5f5-4214-43f6-99c1-883f275e6b09"},"_deposit":{"id":"223481","pid":{"type":"depid","value":"223481","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"マルチFPGA上でのVision Transformerの並列実装","author_link":["588601","588603","588602"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチFPGA上でのVision Transformerの並列実装"},{"subitem_title":"Parallel Implementation of Vision Transformer on Multi FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"設計技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-01-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"},{"subitem_text_value":"慶應義塾大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/223481/files/IPSJ-SLDM23201006.pdf","label":"IPSJ-SLDM23201006.pdf"},"date":[{"dateType":"Available","dateValue":"2025-01-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23201006.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2f446e22-9ce4-4dd2-bc1b-0d19f2630871","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"福嶋, 泰優"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯塚, 健介"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々の研究室では，M-KUBOS と呼ばれる価格性能比に優れた Zynq ボード複数枚から構成されるマルチ FPGA システムである，M-KUBOS クラスタを開発している．M-KUBOS クラスタは，5G モバイルネットワーク向けのマルチアクセスエッジコンピューティング（MEC）のサーバとしての利用が期待されており，近年需要が高まっている深層学習のように計算量，パラメータ数が膨大な処理を高性能，高電力効率で実行できることが求められる．深層学習の中でも，Vision Transformer（ViT）は，画像認識タスクにおいて畳み込み演算を用いずに高い認識精度を達成したことで注目されているが，その計算量とパラメータ数は非常に膨大であり，M-KUBOS クラスタで用いられているようなミドルエンドの FPGA 単体で高性能を達成することは困難である．そこで本研究では，M-KUBOS クラスタの FPGA 複数枚を用いて ViT の推論アクセラレータを実装した．ボード間パイプライン処理によって，使用する FPGA ボードの枚数に応じた線形的な性能向上を実現し，本実装は最大で 704GOPS の性能と 12.4GOPS/W の電力効率を達成した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"10","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-01-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"6","bibliographicVolumeNumber":"2023-SLDM-201"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":223481,"updated":"2025-01-19T13:23:31.005853+00:00","links":{},"created":"2025-01-19T01:23:20.620228+00:00"}