{"updated":"2025-01-19T13:23:36.803643+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00223476","sets":["1164:2036:11089:11090"]},"path":["11090"],"owner":"44499","recid":"223476","title":["高位合成ツールCyberWorkBenchを用いたマルチFPGA設計環境"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-01-16"},"_buckets":{"deposit":"824c3d75-3384-4d98-bb1b-ea9e368c80a1"},"_deposit":{"id":"223476","pid":{"type":"depid","value":"223476","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"高位合成ツールCyberWorkBenchを用いたマルチFPGA設計環境","author_link":["588557","588560","588559","588558","588561","588563","588564","588562"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高位合成ツールCyberWorkBenchを用いたマルチFPGA設計環境"},{"subitem_title":"Multi-FPGA design environment using CyberWorkBench, a high-level synthesis tool","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位合成と配置配線","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-01-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"日本電気株式会社"},{"subitem_text_value":"東京大学工学系研究科付属システムデザイン研究センター"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"NEC","subitem_text_language":"en"},{"subitem_text_value":" University of Tolyo System Design Lab","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/223476/files/IPSJ-SLDM23201001.pdf","label":"IPSJ-SLDM23201001.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23201001.pdf","filesize":[{"value":"2.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"28e64850-7d9d-457c-a74a-fd7425fc47c4","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"鈴木, 裕章"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高橋, 渡"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"若林, 一敏"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroaki, Suzuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Wataru, Takahashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazutoshi, Wakabayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"複数の FPGA ボードを直接高速シリアルリンクで接続したマルチ FPGA システムは，MEC (Multi-edge access Computing) 用の計算ノードとして注目されているが，マルチ FPGA システムでの開発ではアプリケーションの分割を人力で行わなくてはならない．また，分割後もボード間の通信路を設定するテーブルを人手で作る必要があり，使用するボードによって通信路の経路が変わってしまう場合には，その都度変更する必要がある．本稿ではマルチ FPGA システム MKUBOS クラスタを対象として，高位合成ツール CyberWorkbench(CWB) と SystemC を用いてアプリケーションの分割及び，実機実装時に使用する通信路設定テーブルの自動生成を行うことで，マルチ FPGA ボード設計環境のフローを改善した．LeNet のプログラムを実装し，手動で分割時に 78.890[ms]，改善された設計フローを使用した場合に 78.892[ms] という評価を得て，手動で分割した場合に対しても性能が落ちず，設計フローを使用することで手間と時間が節約できることを示した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-01-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2023-SLDM-201"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:23:20.334584+00:00","id":223476,"links":{}}