{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00222444","sets":["1164:2036:10820:11033"]},"path":["11033"],"owner":"44499","recid":"222444","title":["帯域内位相雑音の低減に向けた3次MASH型∆ΣFDCに基づくデジタル位相同期回路の設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-11-21"},"_buckets":{"deposit":"49273c6f-12ff-4004-9eca-40d122803730"},"_deposit":{"id":"222444","pid":{"type":"depid","value":"222444","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"帯域内位相雑音の低減に向けた3次MASH型∆ΣFDCに基づくデジタル位相同期回路の設計","author_link":["583712","583706","583707","583701","583710","583703","583702","583708","583704","583711","583705","583709"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"帯域内位相雑音の低減に向けた3次MASH型∆ΣFDCに基づくデジタル位相同期回路の設計"},{"subitem_title":"Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ∆Σ FDC for Low In-Band Phase Noise","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ハードウェアデザイン","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-11-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科電気系工学専攻"},{"subitem_text_value":"東京大学大学院工学系研究科附属システムデザイン研究センター"},{"subitem_text_value":"東京大学大学院工学系研究科電気系工学専攻"},{"subitem_text_value":"東京大学大学院工学系研究科電気系工学専攻"},{"subitem_text_value":"東京大学大学院工学系研究科電気系工学専攻"},{"subitem_text_value":"東京大学大学院工学系研究科電気系工学専攻／東京大学大学院工学系研究科附属システムデザイン研究センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept.of Electrical Engineering and Information Systems, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Systems Design Lab., School of Engineering, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept.of Electrical Engineering and Information Systems, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept.of Electrical Engineering and Information Systems, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept.of Electrical Engineering and Information Systems, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept.of Electrical Engineering and Information Systems, The University of Tokyo / Systems Design Lab., School of Engineering, The University of Tokyo ","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/222444/files/IPSJ-SLDM22200025.pdf","label":"IPSJ-SLDM22200025.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM22200025.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"8d5caf67-afc6-4265-8a2d-ffc123d723c7","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"岩下, 僚我"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"徐, 祖楽"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"長田, 将"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柴田, 凌弥"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"熊野, 陽"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯塚, 哲也"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryoga, Iwashita","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Zule, Xu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaru, Osada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ryoya, Shibata","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yo, Kumano","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tetsuya, Iizuka","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"∆Σ FDC-PLL は ∆Σ 変調により低域の量子化雑音低減が可能な PLL であるが，帯域幅を狭くする必要がある．本論文では MASH を用いたより高い次数の ∆Σ FDC-PLL の設計方法を提案している．提案手法により従来よりも帯域内の量子化雑音が低減され，ループの最適化をより柔軟に行うことができる．設計には 65nm LP CMOS プロセスを用い，従来の構成に 3bit SAR ADC と ∆Σ ADC を加え実装した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"∆Σ frequency-to-digital converter based phase locked loops (FDC-PLLs) can reduce its quantization noise at low frequency by ∆Σ modulation. However, it requires narrow PLL bandwidth. This paper proposes the method to design higher-order ∆Σ FDC-PLLs by applying multi-stage noise shaping (MASH). The proposed PLLs can make in-band quantization noise lower than that of conventional FDC-PLLs , which enables more flexible loop optimization. The proposed PLL is designed in 65 nm CMOS process using 3bit SAR ADC and a ∆Σ ADC.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-11-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"25","bibliographicVolumeNumber":"2022-SLDM-200"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:22:23.982490+00:00","updated":"2025-01-19T13:44:55.601878+00:00","id":222444}