@techreport{oai:ipsj.ixsq.nii.ac.jp:00222444,
 author = {岩下, 僚我 and 徐, 祖楽 and 長田, 将 and 柴田, 凌弥 and 熊野, 陽 and 飯塚, 哲也 and Ryoga, Iwashita and Zule, Xu and Masaru, Osada and Ryoya, Shibata and Yo, Kumano and Tetsuya, Iizuka},
 issue = {25},
 month = {Nov},
 note = {∆Σ FDC-PLL は ∆Σ 変調により低域の量子化雑音低減が可能な PLL であるが，帯域幅を狭くする必要がある．本論文では MASH を用いたより高い次数の ∆Σ FDC-PLL の設計方法を提案している．提案手法により従来よりも帯域内の量子化雑音が低減され，ループの最適化をより柔軟に行うことができる．設計には 65nm LP CMOS プロセスを用い，従来の構成に 3bit SAR ADC と ∆Σ ADC を加え実装した．, ∆Σ frequency-to-digital converter based phase locked loops (FDC-PLLs) can reduce its quantization noise at low frequency by ∆Σ modulation. However, it requires narrow PLL bandwidth. This paper proposes the method to design higher-order ∆Σ FDC-PLLs by applying multi-stage noise shaping (MASH). The proposed PLLs can make in-band quantization noise lower than that of conventional FDC-PLLs , which enables more flexible loop optimization. The proposed PLL is designed in 65 nm CMOS process using 3bit SAR ADC and a ∆Σ ADC.},
 title = {帯域内位相雑音の低減に向けた3次MASH型∆ΣFDCに基づくデジタル位相同期回路の設計},
 year = {2022}
}