{"created":"2025-01-19T01:22:23.115609+00:00","updated":"2025-01-19T13:45:12.376751+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00222429","sets":["1164:2036:10820:11033"]},"path":["11033"],"owner":"44499","recid":"222429","title":["自律駆動DMAエンジンを搭載したFPGA演算システム"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-11-21"},"_buckets":{"deposit":"1acb7eda-771e-4aae-87ab-9c97a15df3ed"},"_deposit":{"id":"222429","pid":{"type":"depid","value":"222429","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"自律駆動DMAエンジンを搭載したFPGA演算システム","author_link":["583591","583589","583597","583590","583598","583593","583594","583596","583592","583595"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"自律駆動DMAエンジンを搭載したFPGA演算システム"},{"subitem_title":"FPGA-based Accelerators System with Autonomous DMA Engine","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGAコンピューティング","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-11-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"NTT ソフトウェアイノベーションセンタ"},{"subitem_text_value":" NTT ソフトウェアイノベーションセンタ(現：NTT コミュニケーションズ)"},{"subitem_text_value":"NTT 先端集積デバイス研究所"},{"subitem_text_value":"NTT 先端集積デバイス研究所"},{"subitem_text_value":"NTT ソフトウェアイノベーションセンタ"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"NTT Software Innovation Center","subitem_text_language":"en"},{"subitem_text_value":" NTT Software Innovation Center (Current: NTT Communications)","subitem_text_language":"en"},{"subitem_text_value":"NTT Device Technology Laboratories","subitem_text_language":"en"},{"subitem_text_value":"NTT Device Technology Laboratories","subitem_text_language":"en"},{"subitem_text_value":"NTT Software Innovation Center","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/222429/files/IPSJ-SLDM22200010.pdf","label":"IPSJ-SLDM22200010.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM22200010.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"8bb278e9-b0b6-4b93-a173-b8550a9e6e79","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"横野, 智也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山部, 芳朗"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"田仲, 顕至"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"有川, 勇輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"石崎, 晃朗"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tomoya, Yokono","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshiro, Yamabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kenji, Tanaka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuki, Arikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Teruaki, Ishizaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，様々な情報処理基盤は性能及び効率を向上させるために，FPGA，GPU や ASIC を用いた特殊なアクセラレータで構成されるケースが増加している．本研究では複数の FPGA と CPU 間の通信及び複数 FPGA への非同期的な処理のオフロードのためにキューを用いた機構を提案する．本論文では，性能及びデータ転送効率を向上させるために，自律駆動 DMA エンジンを搭載した FPGA を含むシステムについて述べる．本システムでは 8 基の FPGA を備えるマシンを構築し，ソフトウェアスタックを含めた 1 基の FPGA の通信性能及び複数の FPGA 間の通信チェインの性能を評価した．1 基のFPGA において，PCIe の理論性能に対してDMA Read 及びDMA Write のバンド幅はそれぞれ 68.5%，62.2% に達し，従来手法と比較してそれぞれ最大約 11 倍，5 倍の性能向上を確認した．8 基の FPGA を用いた通信チェインでは，4MB のデータサイズの転送レイテンシは 3.7 ミリ秒であり，既存の DMA 手法と比較し半分以下のレイテンシであった．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-11-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"10","bibliographicVolumeNumber":"2022-SLDM-200"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":222429,"links":{}}