{"id":222427,"updated":"2025-01-19T13:45:14.523652+00:00","links":{},"created":"2025-01-19T01:22:22.997969+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00222427","sets":["1164:2036:10820:11033"]},"path":["11033"],"owner":"44499","recid":"222427","title":["RTL故障診断容易化設計に基づくテスト生成法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-11-21"},"_buckets":{"deposit":"265e23a1-a827-4c38-88fb-61bb9d93d008"},"_deposit":{"id":"222427","pid":{"type":"depid","value":"222427","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"RTL故障診断容易化設計に基づくテスト生成法","author_link":["583578","583581","583579","583580","583582","583577"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"RTL故障診断容易化設計に基づくテスト生成法"},{"subitem_title":"A Test Generation Merhod Based on Design for Diagnosability at RTL","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高信頼LSIテスト技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-11-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日本大学大学院生産工学研究科"},{"subitem_text_value":"日本大学生産工学部"},{"subitem_text_value":"明治大学情報コミュニケーション学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Industrial Technology Nihon University","subitem_text_language":"en"},{"subitem_text_value":"College of Industrial Technology Nihon University","subitem_text_language":"en"},{"subitem_text_value":" School of Information and Communication Meji University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/222427/files/IPSJ-SLDM22200008.pdf","label":"IPSJ-SLDM22200008.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM22200008.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"9b3b803c-892a-493a-9cee-970f74146f84","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"千田, 祐弥"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"細川, 利典"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山崎, 浩二"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuya, Chida","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshinori, Hosokawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kouji, Yamazaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"故障診断において，高故障検出率かつ多数の故障ペアが識別可能であることが重要である．このことを実現するために，レジスタ転送レベル回路における故障診断容易化設計のためのコントローラの制御信号のドントケア割当て法が提案されている．しかしながら，診断容易化設計が適用されたレジスタ転送レベル回路を論理合成し，スキャン設計を施して生成された論理回路に対してテスト生成を実行しても，診断容易化設計での診断分解能向上の意図が考慮されていないため，必ずしも高い診断分解能が得られるとは限らない．本論文では，診断分解能向上のために診断容易化設計が施された回路に対して診断容易化設計情報を抽出した後，その情報を用いたテスト生成法を提案し，多数の故障ペアを識別可能なテスト集合が生成されることを示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In fault diagnosis, it is important to achieve high fault coverage and to identify a large number of fault pairs. A don't-care filling method of control signals for controllers as design for diagnosability at register transfer level has been proposed to attain these goals. However, even if test generation is performed on logic circuits generated by applying logic synthesis and scan design to register transfer level circuits with design for diagnosability, the generated test set do not always obtain high diagnosis resolution. Because an ordinary test generation tool does not know the intention to improve diagnosis resolution at the design. In this paper, after extracting the design for diagnosability information from circuits with design for diagnosability, we propose a test generation method using the information and show that a generated test set can identify a large number of fault pairs.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-11-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicVolumeNumber":"2022-SLDM-200"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}