{"created":"2025-01-19T01:22:22.597193+00:00","updated":"2025-01-19T13:45:22.094160+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00222420","sets":["1164:2036:10820:11033"]},"path":["11033"],"owner":"44499","recid":"222420","title":["FPGA-SoMを用いたASIC試作チップ評価システムの構築"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-11-21"},"_buckets":{"deposit":"3428d16b-e613-4eea-86f9-cb26c91336ae"},"_deposit":{"id":"222420","pid":{"type":"depid","value":"222420","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGA-SoMを用いたASIC試作チップ評価システムの構築","author_link":["583539","583540","583542","583538","583541","583543"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA-SoMを用いたASIC試作チップ評価システムの構築"},{"subitem_title":"Development of ASIC Prototype Chip Evaluation System using FPGA-SoM","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"VLSI設計技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-11-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"弘前大学"},{"subitem_text_value":"東京工業大学"},{"subitem_text_value":"国立情報学研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Hirosaki University","subitem_text_language":"en"},{"subitem_text_value":"Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"National Institute of Informatics","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/222420/files/IPSJ-SLDM22200001.pdf","label":"IPSJ-SLDM22200001.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM22200001.pdf","filesize":[{"value":"3.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"1dedd14a-278d-4a32-8b24-a06197e7f030","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"今井, 雅"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉瀬, 謙二"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"米田, 友洋"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masashi, Imai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kenji, Kise","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tomohiro, Yoneda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ASIC 試作チップの評価には，各チップの仕様に基づいた評価システムが必要であり，汎用性に乏しい．本稿では，FPGA-SoM (System-on-Module) を利用した，汎用的な ASIC 試作チップ評価システムを提案する．提案システムの評価のため設計・製造した，手書き文字判定を行う MNIST AI チップについて紹介し，提案システムで評価した結果を示す．また，設計時に用いたシミュレーション用テストベンチ記述をそのままハードウェア化するハードウェアテストベンチを提案する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"An ASIC prototype chip requires the corresponding evaluation system based on its specification, resulting in lack of versatility. In this paper, we propose a general ASIC prototype chip evaluation system using FPGA-SoM. An MNIST AI chip which recognizes handwritten digit characters is designed and manufactured for the evaluation of the developed system. We also propose a hardware testbench concept in which the testbench descrptions are directly translated into hardware.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-11-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2022-SLDM-200"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":222420,"links":{}}