{"id":220332,"updated":"2025-01-19T14:36:05.936896+00:00","links":{},"created":"2025-01-19T01:20:22.652086+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00220332","sets":["1164:1579:10818:11010"]},"path":["11010"],"owner":"44499","recid":"220332","title":["スケーラブルかつ生産性の高いプログラミングがトランザクショナルメモリに求めるもの"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-10-04"},"_buckets":{"deposit":"15ec6756-95d7-4c7f-8ec3-9805bb6f11c9"},"_deposit":{"id":"220332","pid":{"type":"depid","value":"220332","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"スケーラブルかつ生産性の高いプログラミングがトランザクショナルメモリに求めるもの","author_link":["576114","576111","576113","576110","576112"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"スケーラブルかつ生産性の高いプログラミングがトランザクショナルメモリに求めるもの"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アルゴリズム・トランザクショナルメモリ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-10-04","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"国立情報学研究所"},{"subitem_text_value":"名古屋工業大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya 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和諒"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"二本松, 秀樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"塩谷, 亮太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"五島, 正裕"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"津邑, 公暁"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"トランザクショナルメモリ (TM) は，性能と生産性を両立し得るという特長から，ロックを代替する並行性制御機構として期待されている．TM 処理系の評価のためのベンチマークとしては，STAMP がデファクトスタンダードの地位を確立している．しかし STAMP は，処理系にとって不必要に難易度の高い設定となっていて，TM はロックより性能が低いという印象を与えてきた．STAMP のこのような状況に対して，Nguyen らは Stampede を提案した．Stampede は，極めて高い性能を実現する一方でアプリケーションプログラムの大幅な書き換えを必要とし，性能と生産性を両立できるという TM の優位点を損なっている．そこで本稿では，Stampede の書き換えとそれに伴う TM 機能のアプリケーションプログラムへの移譲について検討する．その結果は，適切な難易度のベンチマークの開発や，Stampede の高性能の要因を取り込んだ処理系の提案につながると期待される．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"12","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-10-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19","bibliographicVolumeNumber":"2022-ARC-250"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}