@techreport{oai:ipsj.ixsq.nii.ac.jp:00220322,
 author = {呉, 吉 and 難波, 一輝 and Wu, Ji and Kazuteru, Namba},
 issue = {9},
 month = {Oct},
 note = {人工知能の技術の進歩に伴い，ニューラルネットワークは，画像の認識において優れた性能を発揮する機械学習として注目されている．高い精度を得るためには大量の演算リソースや消費電力が必要であるため，メモリや消費電力に制限のあるエッジデバイスへの組み込みには課題が存在する．そこで，演算負荷を下げるために，多くの乗算と加算により構成されるニューラルネットワークの演算を低ビット数へ量子化し，AIoT (Artificial  Intelligence  of  Things) など専用のハードウェア上で実行する技術の研究が行われてきた．そこで，本論文では，高電圧および低電圧モードに基づく SRAM を量子化ニューラルネットワークの重みを保存するように提案する．一般的に，ニューラルネットワークを量子化すること及び SRAM の動作電圧を引き下げることで，認識率が低下．両者と認識率の関係を調査し，高い認識率を保ちながら消費電力を引き下げることのできる回路モデルを示す．, With the advancement of artificial intelligence technologies, neural networks have been attracting attention as a machine learning technique that provides superior performance in image recognition. Since high-precision neural network computing inevitably requires enormous computational resources and power consumption, there are challenges in integrating neural networks into edge devices with limited memory and power consumption. Therefore, to reduce the computational load, research has been conducted to quantize neural network operations, which are composed of many multiplications and additions, to a low-bit number and to execute them on dedicated hardware such as AIoT (Artificial Intelligence of Things). In this paper, we propose an SRAM based on high-voltage and low-voltage modes to store the weights of the quantized neural network. In general, quantization of neural networks and lowering the operating voltage of SRAM reduce the recognition accuracy rate. We investigated the relationship between the two operations mentioned above and the recognition accuracy rate. We proposed a circuit model that can lower power consumption while maintaining a high recognition rate.},
 title = {SRAMの動作電圧引き下げによる量子化ニューラルネットワークの低電力化},
 year = {2022}
}