{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00219198","sets":["6164:6165:7651:10964"]},"path":["10964"],"owner":"44499","recid":"219198","title":["物体検出のためのYOLOv4-tinyのFPGA実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-08-24"},"_buckets":{"deposit":"7997db13-2c14-472e-a634-01967260c3a9"},"_deposit":{"id":"219198","pid":{"type":"depid","value":"219198","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"物体検出のためのYOLOv4-tinyのFPGA実装","author_link":["571518","571516","571519","571517"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"物体検出のためのYOLOv4-tinyのFPGA実装"},{"subitem_title":"FPGA Implementation of YOLOv4-tiny for Object Detection","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ポスター","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2022-08-24","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"三重大学大学院工学研究科情報工学専攻"},{"subitem_text_value":"三重大学大学院工学研究科情報工学専攻"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer Engineering, Graduates School of Engineering, Mie University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Engineering, Graduates School of Engineering, Mie University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/219198/files/IPSJ-DAS2022026.pdf","label":"IPSJ-DAS2022026.pdf"},"date":[{"dateType":"Available","dateValue":"2024-08-24"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2022026.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"0ca9011b-9877-46fa-8de3-e3e367e0a956","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"古市, 諒成"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高木, 一義"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryosei, Furuichi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazuyoshi, Takagi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では FPGA を用いた YOLOv4-tiny アクセラレータを提案する．開発ツールとして Xilinx 社が提供する Vitis AI を使用した．物体検出はコンピュータビジョンにおける挑戦的なタスクである．YOLO のような深層学習アルゴリズムでは GPU が広く使用されているが，消費電力と物理的なスペースの面で小規模システムには向かない．そこで本研究では，組込みシステムを対象として FPGA を使用した物体検出システムを提案する．AI 推論用の開発プラットフォームである Vitis AI を用いて，YOLOv4-tiny を組み込み開発ボードの Ultra96v1 に実装した．Vitis AI で提供される DPU（Deep Learning Processor Unit）を使用して畳み込み演算の高速化を図った．DPU は SoC デバイスのプログラマブルロジック（PL）内に 1 つのブロックとして統合され，プロセッシングシステム（PS）に直接接続可能である．物体検出の前処理と後処理を PS で行い，推論部分を PL の DPU で処理する．また，今後の改良手法を提案する．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this study, we propose a YOLOv4-tiny accelerator in an FPGA. We used Vitis AI provided by Xilinx, Inc. as a development tool. Object detection is a challenging task in computer vision, and GPUs are widely used in deep learning algorithms such as YOLO. However they are not suitable for small systems in terms of power consumption and physical space. Therefore, we use FPGAs for embedded systems. We implemented YOLOv4-tiny on an embedded development board Ultra96v1 using Vitis AI, a development platform for AI inference, and used DPU (Deep Learning Processor Unit) provided by Vitis AI to accelerate convolutional operations. The DPU is integrated as a single block in the programmable logic (PL) of the device and can be directly connected to the processing system (PS). The PS performs the pre-processing and post-processing of object detection, while the DPU in the PL handles the inference part. We also propose a method for future improvement.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"156","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2022論文集"}],"bibliographicPageStart":"151","bibliographicIssueDates":{"bibliographicIssueDate":"2022-08-24","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2022"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":219198,"updated":"2025-01-19T14:53:27.063513+00:00","links":{},"created":"2025-01-19T01:19:31.136550+00:00"}