{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00219192","sets":["6164:6165:7651:10964"]},"path":["10964"],"owner":"44499","recid":"219192","title":["8T-SRAMを用いた同時2入力可能な2値化ニューラルネットワーク用インメモリアクセラレータ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-08-24"},"_buckets":{"deposit":"a9f58810-8aaa-4192-8ee6-1a9f44635c19"},"_deposit":{"id":"219192","pid":{"type":"depid","value":"219192","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"8T-SRAMを用いた同時2入力可能な2値化ニューラルネットワーク用インメモリアクセラレータ","author_link":["571495","571492","571491","571494","571496","571493"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"8T-SRAMを用いた同時2入力可能な2値化ニューラルネットワーク用インメモリアクセラレータ"},{"subitem_title":"8T-SRAM based Dual input In-Memory Accelerator for Binarized Neural Network","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"低電力・低エネルギー設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2022-08-24","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/219192/files/IPSJ-DAS2022020.pdf","label":"IPSJ-DAS2022020.pdf"},"date":[{"dateType":"Available","dateValue":"2024-08-24"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2022020.pdf","filesize":[{"value":"1.8 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"29722262-7703-4836-b0e9-7d9b64a4df69","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田形, 寛斗"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐藤, 高史"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"粟野, 皓光"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroto, Tagata","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takashi, Sato","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiromitsu, Awano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では，8T-SRAM を用いた 2 値化ニューラルネットワーク用インメモリアクセラレータを提案する．提案回路は一般的には相補的に利用されるビットラインをそれぞれ独立に用いることで，2 つの入力について XNOR を同時に計算可能とし，積和演算の実行速度を最大 2 倍にした．トランジスタレベル・シミュレーションの結果，93.88% の MNIST 分類精度を達成し，既存研究と比べ消費エネルギーを 29% 削減できることを確認した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes an in-memory accelerator for binarized neural networks using 8T-SRAM. The proposed circuit uses independent bit lines, which are generally used in complementary manner, to simultaneously computeXNOR for two inputs, thus doubling the performance of the sum-of-products operation at the maximum. The transistor-level simulation shows that the proposed circuit achieves 93.88% MNIST classification accuracy while reducing the energy consumption by 29% compared to existing studies.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"125","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2022論文集"}],"bibliographicPageStart":"120","bibliographicIssueDates":{"bibliographicIssueDate":"2022-08-24","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2022"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:19:30.800895+00:00","updated":"2025-01-19T14:53:34.094560+00:00","id":219192}