{"created":"2025-01-19T01:19:30.347679+00:00","updated":"2025-01-19T14:53:45.732270+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00219184","sets":["6164:6165:7651:10964"]},"path":["10964"],"owner":"44499","recid":"219184","title":["オープンソースのアナログ回路自動設計に向けたブロック方式設計のSkywater 130nmプロセスによる実証"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-08-24"},"_buckets":{"deposit":"7c015025-f921-41c1-99c2-ad354f73ebc5"},"_deposit":{"id":"219184","pid":{"type":"depid","value":"219184","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"オープンソースのアナログ回路自動設計に向けたブロック方式設計のSkywater 130nmプロセスによる実証","author_link":["571450","571451","571456","571458","571457","571452","571454","571453","571455","571449"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"オープンソースのアナログ回路自動設計に向けたブロック方式設計のSkywater 130nmプロセスによる実証"},{"subitem_title":"Verification of Block-Baesd Design in Skywater 130-nm Process toward Open-Source Analog Circuit Layout Generator","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路設計支援","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2022-08-24","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"滋賀県立大学"},{"subitem_text_value":"滋賀県立大学"},{"subitem_text_value":"滋賀県立大学"},{"subitem_text_value":"滋賀県立大学"},{"subitem_text_value":"滋賀県立大学"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Shiga Prefecture","subitem_text_language":"en"},{"subitem_text_value":"The University of Shiga Prefecture","subitem_text_language":"en"},{"subitem_text_value":"The University of Shiga Prefecture","subitem_text_language":"en"},{"subitem_text_value":"The University of Shiga Prefecture","subitem_text_language":"en"},{"subitem_text_value":"The University of Shiga Prefecture","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/219184/files/IPSJ-DAS2022012.pdf","label":"IPSJ-DAS2022012.pdf"},"date":[{"dateType":"Available","dateValue":"2024-08-24"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2022012.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"5f6f549f-bd74-4fa3-83bb-95ca271bd167","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"阿南, 椋久"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山下, 太一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"土谷, 亮"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"井上, 敏之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"岸根, 桂路"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Riku, Anan","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Taichi, Yamashita","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Akira, Tuchiya","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshiyuki, Inoue","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Keiji, Kishine","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"集積回路のオープンソース化の動きが加速しており，オープンソースの EDA ツールや PDK が整備されつつある．これにともなって設計資産のオープン化も重要になると考えられる．我々はアナログ回路の自動設計や非熟練者による設計を容易にする技術として，すべての素子および配線を規格化されたブロックとしてレイアウト設計を行なうブロック方式設計を提案している．本論文では，ブロック方式設計をオープンなプロセスである Skywater130nm プロセスに適用した．素子および配線ブロックを適切に設計することにより，ブロック方式設計によって逐次比較型 AD コンバータの設計が可能であることを実証した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Open-source IC design has appeared and some open-source EDA tools and open-source PDKs have been available. We proposed a layout framework called block-based design, which treats all elements and wires as blocks with standardized layout size. The block-based design skips LPE by using block model including parasitics. We expect that the block-based design is suitable for layout generation of analog circuits. On the other hand, block-based design has drawbacks such as area overhead, increase of parasitics, and modeling error. In this paper, we verify the impact of drawbacks by designing SAR-ADC in skywater 130-nm CMOS. Design experiment shows the drawbacks are in reasonable range compared to full-custom layout.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"76","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2022論文集"}],"bibliographicPageStart":"70","bibliographicIssueDates":{"bibliographicIssueDate":"2022-08-24","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2022"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":219184,"links":{}}