{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00219011","sets":["1164:1579:10818:10973"]},"path":["10973"],"owner":"44499","recid":"219011","title":["主記憶帯域使用率向上のためのCGRA タンデム化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-07-20"},"_buckets":{"deposit":"cdc98d60-4c0b-4651-b5e7-46aeaafa349f"},"_deposit":{"id":"219011","pid":{"type":"depid","value":"219011","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"主記憶帯域使用率向上のためのCGRA タンデム化","author_link":["570736","570737"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"主記憶帯域使用率向上のためのCGRA タンデム化"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-07-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"奈良先端科学技術大学院大学先端科学技術研究科"},{"subitem_text_value":"奈良先端科学技術大学院大学先端科学技術研究科"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/219011/files/IPSJ-ARC22249022.pdf","label":"IPSJ-ARC22249022.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22249022.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"5a38982f-8a6c-4670-8569-aa9e8918a3e1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"赤部, 知也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中島, 康彦"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ARM プロセッサをホストとし，AXI インタフェースにより接続される CGRA 型アクセラレータ IMAX2は，AXI トランザクションを使用した IMAX2 のローカルメモリと ARM の主記憶間の DMA に要する時間がボトルネックであった．そこで，DMA の 8 チャネル化と AXI インターフェイスをフルに活用するための IMAX2 のタンデム化を行った．事前転置をしない 7200×7200 の行列積による評価の結果，タンデム化していないユニット数が同じ IMAX2 に対して，ローカルメモリに ARM の主記憶から入力データを書き込む時間は約 45%，全体時間は約 20% の削減を確認した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"4","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-07-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"22","bibliographicVolumeNumber":"2022-ARC-249"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:19:21.006443+00:00","updated":"2025-01-19T14:57:21.938341+00:00","id":219011}