{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00219008","sets":["1164:1579:10818:10973"]},"path":["10973"],"owner":"44499","recid":"219008","title":["Fault-aware Hardware Scheduling of Computations in Deep Neural Networks"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-07-20"},"_buckets":{"deposit":"b873857b-0756-4e76-83ff-0bd8a458bbba"},"_deposit":{"id":"219008","pid":{"type":"depid","value":"219008","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Fault-aware Hardware Scheduling of Computations in Deep Neural Networks","author_link":["570717","570715","570716","570718","570714","570719"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Fault-aware Hardware Scheduling of Computations in Deep Neural Networks"},{"subitem_title":"Fault-aware Hardware Scheduling of Computations in Deep Neural Networks","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"AI技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-07-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Keio University"},{"subitem_text_value":"Keio University"},{"subitem_text_value":"Keio University／RIKEN"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University","subitem_text_language":"en"},{"subitem_text_value":"Keio University / RIKEN","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/219008/files/IPSJ-ARC22249019.pdf","label":"IPSJ-ARC22249019.pdf"},"date":[{"dateType":"Available","dateValue":"2024-07-20"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22249019.pdf","filesize":[{"value":"2.8 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"292d7d42-8d38-4191-b461-a969174e8eba","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shaswot, Shresthamali"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuan, He"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaaki, Kondo"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shaswot, Shresthamali","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuan, He","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaaki, Kondo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"The idea of using inexact computation for overprovisioned DNNs (Deep Neural Networks) to extract power savings and performance gains at the cost of minor performance degradation has become very popular. However, there is still no general method to schedule the DNN computations on a given hardware platform to effectively implement this idea without loss in computational efficiency. Most contemporary methods require extensive retraining, specialized hardware and hardware-specific scheduling schemes. We present HAS: Hardware Agnostic Scheduler for scheduling DNN computations in heterogeneous and faulty hardware. Given a trained DNN model and a hardware fault profile, our scheduler is able to recover significant performance even at high fault rates. HAS schedules the computations such that the low priority ones are allocated to inexact hardware. Since most DNN computations are matrix multiplications, it achieves this by shuffling (exchanging) the rows of the matrices. The best shuffling order for a given DNN model and hardware faulty profile is determined using Genetic Algorithms (GA). We simulate bitwise errors on different model architectures and datasets with different types of fault profiles and observe that HAS can recover up to 30% of classification accuracy even at high fault rates (which correspond to approximately 50% power savings).","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The idea of using inexact computation for overprovisioned DNNs (Deep Neural Networks) to extract power savings and performance gains at the cost of minor performance degradation has become very popular. However, there is still no general method to schedule the DNN computations on a given hardware platform to effectively implement this idea without loss in computational efficiency. Most contemporary methods require extensive retraining, specialized hardware and hardware-specific scheduling schemes. We present HAS: Hardware Agnostic Scheduler for scheduling DNN computations in heterogeneous and faulty hardware. Given a trained DNN model and a hardware fault profile, our scheduler is able to recover significant performance even at high fault rates. HAS schedules the computations such that the low priority ones are allocated to inexact hardware. Since most DNN computations are matrix multiplications, it achieves this by shuffling (exchanging) the rows of the matrices. The best shuffling order for a given DNN model and hardware faulty profile is determined using Genetic Algorithms (GA). We simulate bitwise errors on different model architectures and datasets with different types of fault profiles and observe that HAS can recover up to 30% of classification accuracy even at high fault rates (which correspond to approximately 50% power savings).","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-07-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19","bibliographicVolumeNumber":"2022-ARC-249"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":219008,"updated":"2025-01-19T14:57:25.198134+00:00","links":{},"created":"2025-01-19T01:19:20.837350+00:00"}