{"id":219001,"updated":"2025-01-19T14:57:33.384168+00:00","links":{},"created":"2025-01-19T01:19:20.441342+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00219001","sets":["1164:1579:10818:10973"]},"path":["10973"],"owner":"44499","recid":"219001","title":["FPGAクラスタにおける矩形領域に対するタスク割当手法の検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-07-20"},"_buckets":{"deposit":"9be8cb9f-1856-415d-8f9a-bf367a2da3d4"},"_deposit":{"id":"219001","pid":{"type":"depid","value":"219001","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGAクラスタにおける矩形領域に対するタスク割当手法の検討","author_link":["570679","570677","570674","570676","570678","570675"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAクラスタにおける矩形領域に対するタスク割当手法の検討"},{"subitem_title":"Task allocation methods for square regions of FPGA clusters","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"エッジコンピューティング基盤","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-07-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/219001/files/IPSJ-ARC22249012.pdf","label":"IPSJ-ARC22249012.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22249012.pdf","filesize":[{"value":"2.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"00f77cf1-d465-4478-8527-cf3be57e2b4a","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"稲毛, 琢己"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯塚, 健介"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takumi, Inage","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kensuke, Iizuka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGA クラスタをMEC（Multi-access Edge Computing) に用いる場合は，それぞれのタスクで要求された数のボードを現在利用していないボードに割り付ける必要がある．ここで，通信バンド幅とレイテンシィを一定に保つためには，連続した矩形領域に割り当てる必要がある．現在，利用している手法は，SLA (Scan Line Algorithm) に基づき，MER（Maximum Empty Rectangles) を探索するが，対象が矩形領域に制限されているため，クラスタの利用効率が悪い．本稿ではより柔軟なアルゴリズムを考案し，割り当て効率の向上を試みる．提案する列優先と行優先のハイブリッド方式の利用により，割り当て後のボードの位置を意識しながら連続領域を維持した長方形以外の割り当てを可能とした結果，シミュレーションによると列優先に対し 3%，行優先に対し 12% の総待ち時間の改善が確認された．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-07-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"12","bibliographicVolumeNumber":"2022-ARC-249"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}