{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00219000","sets":["1164:1579:10818:10973"]},"path":["10973"],"owner":"44499","recid":"219000","title":["RISC-V MPおよびSLM再構成ロジックを混載した「SLMLET」チップの予備評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-07-20"},"_buckets":{"deposit":"80e8b857-4d7b-4f7b-9b0d-652367dea77d"},"_deposit":{"id":"219000","pid":{"type":"depid","value":"219000","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"RISC-V MPおよびSLM再構成ロジックを混載した「SLMLET」チップの予備評価","author_link":["570672","570666","570669","570671","570665","570664","570670","570673","570668","570667"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"RISC-V MPおよびSLM再構成ロジックを混載した「SLMLET」チップの予備評価"},{"subitem_title":"Preliminary Evaluation of \"SLMLET\" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"エッジコンピューティング基盤","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-07-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"東京大学大学院情報理工学系研究科"},{"subitem_text_value":"Dept. of ECE, National University of Singapore"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"熊本大学大学院先端科学研究部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ECE, National University of Singapore","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduated School of Advanced Science and Technology, Kumamoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/219000/files/IPSJ-ARC22249011.pdf","label":"IPSJ-ARC22249011.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22249011.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"7962897e-1589-4863-8b01-3c9873758091","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"矢内, 洋祐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小島, 拓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"奥原, 颯"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yosuke, Yanai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takuya, Kojima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hayate, Okuhara","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Iida","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，IoT エッジデバイスにおける処理能力の更なる向上が進んでいる．そこで，FPGA と CPU の混載 SoC というソリューションが注目を集めている．従来の面積・消費電力共に大きなハイエンド混載 SoC ではなく，比較的小型のマイクロプロセッサと組込み FPGA IP である eFPGA (Embedded FPGA) を組み合わせた小型・低消費電力な混載 SoC は既にソリューションとして有効であることが確認されている．我々はこれを踏まえて，熊本大学が開発した SLM (Scalable Logic Module) 再構成ロジックとRISC-V CPU，SRAM および外部 I/F を混載した新たな小型・低消費電力な IoT エッジデバイス向け SoC，SLMLET を開発している．SLM には構成情報量が小さくロジックセルが小型である特徴があり，また RISC-V CPU は小型でオープンソースな実装が多数存在することが特徴である．本稿ではこの SLMLET チップの紹介を行い，および製造前の評価としてチップ間の高速インターフェースとして採用した Hyperbus による SLMLET 間の DMA 転送性能評価を行った．その結果，Hyperbus コントローラを論理合成時の想定速度である 50MHz で動作させた際，1024 バイト以上の転送においてバスの理論値の 90% 以上，またコントローラがサポートしている最大サイズである  65535 バイトの転送においては理論値の 99.9% 以上となる 799.4Mbps が達成できることを確認した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-07-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"11","bibliographicVolumeNumber":"2022-ARC-249"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":219000,"updated":"2025-01-19T14:57:34.436093+00:00","links":{},"created":"2025-01-19T01:19:20.384636+00:00"}