{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00218996","sets":["1164:1579:10818:10973"]},"path":["10973"],"owner":"44499","recid":"218996","title":["単一磁束量子プロセッサ向けキャッシュメモリ構成法の検討と定量的評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-07-20"},"_buckets":{"deposit":"d094672b-5a1b-4ca8-818a-d6cc1fb92b17"},"_deposit":{"id":"218996","pid":{"type":"depid","value":"218996","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"単一磁束量子プロセッサ向けキャッシュメモリ構成法の検討と定量的評価","author_link":["570641","570635","570636","570643","570637","570638","570639","570642","570640"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"単一磁束量子プロセッサ向けキャッシュメモリ構成法の検討と定量的評価"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"新デバイス・新アルゴリズム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-07-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"名古屋大学"},{"subitem_text_value":"九州大学"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/218996/files/IPSJ-ARC22249007.pdf","label":"IPSJ-ARC22249007.pdf"},"date":[{"dateType":"Available","dateValue":"2024-07-20"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22249007.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"5849eb6e-f994-4522-b4b7-836021adb5ab","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"鴨志田, 圭吾"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"石川, 伊織"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"羽野, 祐太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"川上, 哲志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"谷本, 輝夫"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小野, 貴継"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"田中, 雅光"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤巻, 朗"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"井上, 弘士"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では,単一磁束量子(Single Flux Quantum:SFQ)回路を用いたマイクロプロセッサの実現を念頭に,4 kelvin環境下での動作を前提とした極低温キャッシュメモリ構成法を検討する.メモリアレイに関しては SFQ シフトレジスタまたは SRAM での実装,キャッシュ内グローバル配線に関しては SFQ または CMOS 回路での実装を想定する.これらの設計選択肢に基づき,SFQ キャッシュ(SFQ シフトレジスタ型 FIFO メモリと SFQ 回路で実装),CMOS キャッシュ(SRAM と CMOS 回路で実装),ならびに,ハイブリッドキャッシュ(SRAM と SFQ 回路で実装)といった 3 つのアーキテクチャモデルを導入し,モデリングに基づくアクセス時間の評価を行う(ただし,本稿ではデータメモリアレイにのみ着目する).その結果,現行の 1.0 μm プロセスを前提とした場合には,SFQ キャッシュよりもハイブリッドまたは CMOSキャッシュが優れていることが分かった.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"10","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ(ARC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-07-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicVolumeNumber":"2022-ARC-249"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":218996,"updated":"2025-01-19T14:57:39.010082+00:00","links":{},"created":"2025-01-19T01:19:20.159781+00:00"}