{"created":"2025-01-19T01:18:58.056544+00:00","updated":"2025-01-19T15:06:28.753248+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00218612","sets":["1164:2735:10865:10962"]},"path":["10962"],"owner":"44499","recid":"218612","title":["ニューラルネットワーク応用へ向けたアナログCMOS多数決回路のLSI実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-06-20"},"_buckets":{"deposit":"7be7a0c8-118e-4bfd-8f62-00990979a5dc"},"_deposit":{"id":"218612","pid":{"type":"depid","value":"218612","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"ニューラルネットワーク応用へ向けたアナログCMOS多数決回路のLSI実装","author_link":["568966","568964","568965","568970","568962","568969","568963","568968","568959","568967","568961","568960"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ニューラルネットワーク応用へ向けたアナログCMOS多数決回路のLSI実装"},{"subitem_title":"LSI implementation of analog CMOS majority circuit for neural network applications","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2022-06-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東北大学大学院工学研究科／東北大学電気通信研究所"},{"subitem_text_value":"東北大学大学院工学研究科"},{"subitem_text_value":"東北大学大学院工学研究科／東北大学電気通信研究所"},{"subitem_text_value":"東北大学大学院工学研究科／東北大学電気通信研究所"},{"subitem_text_value":"群馬大学理工学府"},{"subitem_text_value":"東北大学大学院工学研究科／東北大学電気通信研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Engineering, Tohoku University/Research Institute of Electrical Communication, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Research Institute of Electrical Communication, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Tohoku University/Research Institute of Electrical Communication, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Tohoku University/Research Institute of Electrical Communication, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Gunma University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Tohoku University/Research Institute of Electrical Communication, Tohoku University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/218612/files/IPSJ-MPS22138042.pdf","label":"IPSJ-MPS22138042.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-MPS22138042.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"17"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"e8cf0c73-c5e7-4e74-9a90-2e5d75773477","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小野, 哲史"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"守谷, 哲"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"菅家, 由佳"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山本, 英明"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"弓仲, 康史"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐藤, 茂雄"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Satoshi, Ono","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Satoshi, Moriya","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuka, Kanke","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideaki, Yamamoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yasushi, Yuminaka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shigeo, Sato","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10505667","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8833","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"多数決回路は複数の 0 または 1 の入力に対して多数を占める値を出力する回路である．多数決回路はバイナリニューラルネットワークやリザバーコンピューティングへの応用が可能である．多数決論理をアナログ回路実装した場合，入力数 N に対して約 4N 個のトランジスタのみで構成することができ，デジタル回路実装した場合よりも大幅に回路規模を削減できる．本研究では 0.18 µm CMOS 技術を用いて実装したアナログ多数決回路の測定を行い，N=11，101 の回路について正確に多数決動作が行われることを確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. It can be applied to binarized neural networks and reservoir computing. When majority logic is implemented in analog circuits, only about 4N transistors are needed for N inputs, and thus the circuit area is significantly reduced in comparison to a digital circuit implementation. In this study, we implemented analog majority logic circuits using 0.18 µm CMOS technology. We measured the circuits with N = 11 and 101 and confirmed that they properly operated. ","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"4","bibliographic_titles":[{"bibliographic_title":"研究報告数理モデル化と問題解決（MPS）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-06-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"42","bibliographicVolumeNumber":"2022-MPS-138"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":218612,"links":{}}