{"id":217265,"updated":"2025-01-19T15:33:45.082225+00:00","links":{},"created":"2025-01-19T01:17:45.992682+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00217265","sets":["1164:2822:10894:10895"]},"path":["10895"],"owner":"44499","recid":"217265","title":["多様なトランザクショナルメモリ実装のスケーラブルなプログラムを用いた定量的比較"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-03-03"},"_buckets":{"deposit":"77f293ea-180b-4595-b743-96c8b252c40b"},"_deposit":{"id":"217265","pid":{"type":"depid","value":"217265","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"多様なトランザクショナルメモリ実装のスケーラブルなプログラムを用いた定量的比較","author_link":["562640","562638","562637","562642","562641","562636","562639"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"多様なトランザクショナルメモリ実装のスケーラブルなプログラムを用いた定量的比較"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリ・アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-03-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"国立情報学研究所"},{"subitem_text_value":"名古屋工業大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya 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秀樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山本, 和諒"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"浅井, 優太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山下, 淳"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"塩谷, 亮太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"五島, 正裕"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"津邑, 公暁"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-868X","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ロックを補完・代替する並行性制御機構としてトランザクショナルメモリ（Transactional Memory: TM）が期待されている．今日までに多様な TM 実装が提案されているが，TM の活用は未だ一般に普及していない．その要因に，TM の性能を引き出すための知見が十分蓄積されていないことや，TM の性能が不十分であることが挙げられる．その点を解決するような研究として，仲池らは，TM のハードウェア実装であるハードウェアトランザクショナルメモリ（Hardware Transactional Memory: HTM）の定量的比較を通じて，次世代 HTM 機構のあるべき姿について議論している．しかし，TM のソフトウェア実装であるソフトウェアトランザクショナルメモリ（Software Transactional Memory: STM）が評価対象に含まれていない上，さまざまな問題点が指摘されているベンチマークを使用した評価に基づいている点で，包括的な TM システムの再検討には十分ではない．そこで本論文では，STM と HTM の両方を評価対象とし，さらに，性能がスケールするよう TM に適した形に改良を施したベンチマークを併用し，定量的比較を行う．TM の実装およびプログラムの差異が性能に与える影響を調査・解析し，TM の性能を引き出すプログラミングや TM システムが備えるべき機能・特徴を議論する．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"10","bibliographic_titles":[{"bibliographic_title":"研究報告組込みシステム（EMB）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-03-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"45","bibliographicVolumeNumber":"2022-EMB-59"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}