{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00217248","sets":["1164:2822:10894:10895"]},"path":["10895"],"owner":"44499","recid":"217248","title":["疎行列演算高速化のためのメモリアーキテクチャ探索"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-03-03"},"_buckets":{"deposit":"48ebbdea-9d5a-4274-a76a-aa28498e4a2f"},"_deposit":{"id":"217248","pid":{"type":"depid","value":"217248","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"疎行列演算高速化のためのメモリアーキテクチャ探索","author_link":["562554","562546","562553","562552","562555","562551","562550","562547","562548","562549"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"疎行列演算高速化のためのメモリアーキテクチャ探索"},{"subitem_title":"Memory architecture exploration for sparse matrix-vector multiplication","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"設計技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-03-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"東京工業大学"},{"subitem_text_value":"東京工業大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Fujitsu ltd.","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu ltd.","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu ltd.","subitem_text_language":"en"},{"subitem_text_value":"Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/217248/files/IPSJ-EMB22059028.pdf","label":"IPSJ-EMB22059028.pdf"},"date":[{"dateType":"Available","dateValue":"2024-03-03"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB22059028.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"df585c64-e69d-442a-b9a2-51b6664a249a","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"萩原, 汐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"児玉, 宏喜"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉川, 隆英"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"幸, 朋矢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"遠藤, 敏夫"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shiho, Hagiwara","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroyoshi, Kodama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takahide, Yoshikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tomoya, Yuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tosio, Endo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-868X","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年のハイパフォーマンスコンピューティングでは，演算速度よりデータ転送速度がボトルネックとなってきている．ボトルネックを解消するには，ハードウェアによる手法とソフトウェアによる手法を適切に組み合わせる必要があるが，どのように組み合わせれば効果的に高速化できるかは明らかではない．特に，疎データを扱うワークロードではメモリアクセスにランダム性があることから解析的に実効性能を求めることが困難であり，高速化の効果を定量的に見積もることは難しい．東京工業大学が開発している PMNet (Performance predictor of Memory Network) では，実際にワークロードを実行した際のトレース結果を使って，任意のメモリアーキテクチャにおける実行時間を推定する．PMNet を使えば，メモリアクセスを考慮したメモリアーキテクチャの性能を高速に見積もることができる．本報告の目的は，疎行列演算を扱うワークロードの実効性能を向上させるための設計指針を立てることである．まず，疎行列ベクトル積 (SpMV; Sparse Matrix-Vector multiplication) を使った PMNet の精度検証を行い，目的達成に十分な精度をもつことを示す．更に，IRDS ロードマップのデバイスパラメタを使って，PMNet がターゲットとしている 2028 年に実現可能なプロセッサにおける SpMV の性能を推測すると共に，高速化のための設計指針を検討する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In recent high-performance computing, data transfer speed has become the bottleneck rather than computation speed. The solution to this problem can be hardware or software. However, it is unclear how to combine them to achieve effective speedup. In particular, for sparse workloads, the randomness of memory access makes it difficult to estimate the computational performance analytically. PMNet (Performance prediction of Memory Network), developed by Tokyo Institute of Technology, estimates the performance of any memory architecture using the memory trace results of actual workload execution. It can quickly evaluate the performance of a memory architecture while considering memory accesses. This report aims to provide design guidelines for improving the performance of sparse matrix operations. First, we conduct accuracy verification using sparse matrix-vector multiplication (SpMV) workloads and show that PMNet has enough accuracy for our aims. Next, we estimate SpMV performance on 2028's processors using PMNet and the device parameters of the IRDS roadmap and discuss design guidelines to accelerate it.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"9","bibliographic_titles":[{"bibliographic_title":"研究報告組込みシステム（EMB）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-03-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"28","bibliographicVolumeNumber":"2022-EMB-59"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":217248,"updated":"2025-01-19T15:34:07.323875+00:00","links":{},"created":"2025-01-19T01:17:45.019474+00:00"}