{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00217231","sets":["1164:2822:10894:10895"]},"path":["10895"],"owner":"44499","recid":"217231","title":["SLM細粒度再構成ロジックにおける構成情報の圧縮"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-03-03"},"_buckets":{"deposit":"39758ba8-1ee5-4f93-b469-906c92a0fb82"},"_deposit":{"id":"217231","pid":{"type":"depid","value":"217231","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"SLM細粒度再構成ロジックにおける構成情報の圧縮","author_link":["562458","562448","562457","562456","562459","562452","562462","562451","562460","562447","562455","562454","562461","562450","562453","562449"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"SLM細粒度再構成ロジックにおける構成情報の圧縮"},{"subitem_title":"Configuration Data Compression for SLM Fine-grained Reconfigurable Logic","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA・再構成可能アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-03-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"熊本大学大学院自然科学教育部"},{"subitem_text_value":"熊本大学大学院先端科学研究部"},{"subitem_text_value":"熊本大学大学院先端科学研究部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduated School of Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduated School of Advanced Science and Technology, Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduated School of Advanced Science and Technology, Kumamoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/217231/files/IPSJ-EMB22059011.pdf","label":"IPSJ-EMB22059011.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB22059011.pdf","filesize":[{"value":"1.8 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"d7ca394a-e5e1-4b4c-95c3-547818b565ed","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"高木, 颯平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"丹羽, 直也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"四釡, 快弥"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"矢内, 洋祐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中里, 優弥"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"尼崎, 太樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Souhei, Takagi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naoya, Niwa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshiya, Shikama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yosuke, Yanai","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuya, Nakazato","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Motoki, Amagasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Iida","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-868X","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"SLM (Scalable Logic Module) は,熊本大学が開発した細粒度再構成ロジックであり,構成情報量が小さく,これによりロジックセルの面積も小さい特徴がある.我々は,この SLM,CPU,スイッチ,メモリを内蔵した新しい FPGA を開発している.このチップでは SLM の構成情報量の小ささを利用し,内部メモリ上に複数の構成情報を蓄え,高速に入れ替える機能を持つ.本稿では,構成情報を圧縮することで,さらに多くの構成情報データを格納するための手法を提案する.この圧縮法は,チップ内部で高速に伸長が可能であり,簡単なハードウェアで実装が可能でなければならない.また,対象となる SLM 再構成ロジックの構成情報は,全体としては 0 の連続が多いが,局所的には 0 と 1 が混ざった部分が存在する.本稿では上記の条件に適合した Run Length 圧縮法である TLC(Tag-Less Compression)を提案する.TLC は,0 の並びに特化し,多くの RunLength 法と異なりタグ(プリフィクス)を必要とせず,実装が極めて容易である.Verilog-HDL により伸長回路を設計し,USJC 55nm プロセスを想定して Synopsys 社デザインコンパイラで論理合成を行った.その結果,793µ????2 というきわめて小さな回路面積であることがわかった.また,回路の遅延は 3095psec であり,200MHz で動作するコンフィギュレーション回路に組み込んで利用可能であることがわかった.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告組込みシステム(EMB)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-03-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"11","bibliographicVolumeNumber":"2022-EMB-59"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":217231,"updated":"2025-01-19T15:34:26.196022+00:00","links":{},"created":"2025-01-19T01:17:44.043983+00:00"}