{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00217219","sets":["1164:2036:10820:10893"]},"path":["10893"],"owner":"44499","recid":"217219","title":["遺伝的アルゴリズムを用いた再構成可能アーキテクチャのソフトウェアパイプライン最適化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-03-03"},"_buckets":{"deposit":"098b7c33-46f6-4a44-8065-15deadd8c2c1"},"_deposit":{"id":"217219","pid":{"type":"depid","value":"217219","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"遺伝的アルゴリズムを用いた再構成可能アーキテクチャのソフトウェアパイプライン最適化","author_link":["562392","562390","562391","562387","562393","562389","562394","562388"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"遺伝的アルゴリズムを用いた再構成可能アーキテクチャのソフトウェアパイプライン最適化"},{"subitem_title":"GA-based Software Pipeline Scheduling for CGRAs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"検証・スケジューリング","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-03-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/217219/files/IPSJ-SLDM22198065.pdf","label":"IPSJ-SLDM22198065.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM22198065.pdf","filesize":[{"value":"2.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"6df01f01-5ea2-4016-8172-1f35225dc239","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中川, 雅人"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小島, 拓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高瀬, 英希"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中村, 宏"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masato, Nakagawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takuya, Kojima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideki, Takase","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroshi, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"粗粒度再構成可能アーキテクチャ CGRA (Coarse-Grained Reconfigurable Architecture) は高い処理性能と省電力性とプログラミングの柔軟性の 3 つの要素を同時に兼ね備えたプロセッサとして近年注目を集めている．CGRA はALU ベースのPE (Processing Element) が 2 次元のアレイ状に配置されメッシュ状のネットワークを形成している．CGRA は，その構造ゆえにストリーム処理を得意としている．ストリーム処理は，DFG (Data Flow Graph) で表現でき，DFG を CGRA の PE に配置する手法として遺伝的アルゴリズムを用いたマッピング手法に GenMap がある．これは多目的最適化を行うことができるが，空間的マッピングしか行えず，1 サイクルごとに再構成を行う動的再構成をサポートしていない．そこで，本研究では動的再構成に対応させ，ソフトウェアパイプライン最適化ができるように GenMap を拡張した．評価の結果，最大で約 45% のスループット向上が得られるマッピングが得られた．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-03-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"65","bibliographicVolumeNumber":"2022-SLDM-198"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":217219,"updated":"2025-01-19T15:34:40.744099+00:00","links":{},"created":"2025-01-19T01:17:43.353719+00:00"}