{"id":217200,"updated":"2025-01-19T15:35:09.387456+00:00","links":{},"created":"2025-01-19T01:17:42.261868+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00217200","sets":["1164:2036:10820:10893"]},"path":["10893"],"owner":"44499","recid":"217200","title":["分散トランザクショナルメモリのためのソフトウェアキャッシュの設計と実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-03-03"},"_buckets":{"deposit":"62cbb9e9-37b3-4478-bd5b-26500f214197"},"_deposit":{"id":"217200","pid":{"type":"depid","value":"217200","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"分散トランザクショナルメモリのためのソフトウェアキャッシュの設計と実装","author_link":["562294","562297","562295","562296","562298","562300","562299"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"分散トランザクショナルメモリのためのソフトウェアキャッシュの設計と実装"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリ・アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-03-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"国立情報学研究所"},{"subitem_text_value":"名古屋工業大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya 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淳"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"二本松, 秀樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山本, 和諒"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"浅井, 優太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"塩谷, 亮太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"五島, 正裕"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"津邑, 公暁"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"現代の科学技術分野の進歩を支える高性能な大規模並列計算基盤は分散メモリ型と呼ばれるハードウェアの形態を取る.この形態を前提としたシステムでは,高性能なプログラムを実現するために,長い期間を費やして手動でチューニングする必要があり,生産性が問題となっている.このような中,生産性と性能を両立しうる機構としてトランザクショナルメモリ(TM)への関心が高まっている.TM はマルチコアプロセッサ向けに多く研究されてきたが,この機構を分散システムにも適用することで,分散メモリ型におけるプログラミングを単純にすることも可能であるという考えから,分散システムを対象とする分散トランザクショナルメモリ(DTM)が提案されているが,実用的な実装は未だ存在していない.我々は生産性と性能を両立する大規模並列計算基盤を実現するため DTM に着目し,生産性の高いプロトタイプを開発したが,性能面に改善の余地がある.そこで本稿では,DTM の性能を高めるためのソフトウェアキャッシュを設計および実装する.提案する DTM システムの有効性を確認するため,マイクロベンチマークおよび STAMP ベンチマークを用いて評価した結果,プロトタイプと比較してマイクロベンチマークでは 1.56倍,STAMP では 3.64 倍の高速化を確認した.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"13","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術(SLDM)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-03-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"46","bibliographicVolumeNumber":"2022-SLDM-198"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}