{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00217107","sets":["1164:1579:10818:10892"]},"path":["10892"],"owner":"44499","recid":"217107","title":["次世代高性能計算ノードに向けたメモリアーキテクチャ探索のためのツールチェーン"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-03-03"},"_buckets":{"deposit":"c9eb2de5-8410-41cf-a5eb-d405f4cce39f"},"_deposit":{"id":"217107","pid":{"type":"depid","value":"217107","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"次世代高性能計算ノードに向けたメモリアーキテクチャ探索のためのツールチェーン","author_link":["561792","561791"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"次世代高性能計算ノードに向けたメモリアーキテクチャ探索のためのツールチェーン"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリ・アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-03-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学学術国際情報センター"},{"subitem_text_value":"東京工業大学学術国際情報センター"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/217107/files/IPSJ-ARC22248019.pdf","label":"IPSJ-ARC22248019.pdf"},"date":[{"dateType":"Available","dateValue":"2024-03-03"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22248019.pdf","filesize":[{"value":"1.9 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"a13d7ed7-7d37-4ed2-97c1-5340969f479c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"幸, 朋矢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"遠藤, 敏夫"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"半導体微細化による性能向上が物理的に難しくなるなか，近年高性能計算ノードでは異種メモリの採用やチップレットによるキャッシュの導入などによって性能向上を狙う例が散見される．今後もこのノード内アーキテクチャデザインの複雑化はさらに進むと考えられるが，そこで重要となるのが，考案したデザインが種々のワークロードにおいてどのように動作するか，どの程度の性能が得られるかを推定するツールである．本稿では，既存のサイクルアキュレートシミュレータと比較してより軽量で扱いやすいメモリシステム性能推定ツール PMNet と，幅広いアーキテクチャトポロジーを表現可能な GUI ツール DAT Viewer を中心としたツールチェーンについて報告する．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"9","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-03-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19","bibliographicVolumeNumber":"2022-ARC-248"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":217107,"updated":"2025-01-19T15:37:12.994444+00:00","links":{},"created":"2025-01-19T01:17:36.792774+00:00"}