{"id":217097,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00217097","sets":["1164:1579:10818:10892"]},"path":["10892"],"owner":"44499","recid":"217097","title":["回線交換マルチFPGAシステムにおけるアプリケーションマッピングツールの実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-03-03"},"_buckets":{"deposit":"00612be4-aea2-4020-92af-1c120b61bb14"},"_deposit":{"id":"217097","pid":{"type":"depid","value":"217097","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"回線交換マルチFPGAシステムにおけるアプリケーションマッピングツールの実装","author_link":["561745","561741","561746","561744","561742","561743"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"回線交換マルチFPGAシステムにおけるアプリケーションマッピングツールの実装"},{"subitem_title":"Implementation of an Application Mapping Tool for a Circuit-Switched Multi-FPGA System","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA・再構成可能アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-03-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/217097/files/IPSJ-ARC22248009.pdf","label":"IPSJ-ARC22248009.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22248009.pdf","filesize":[{"value":"2.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"20bfa0d7-e4b9-4478-96a6-df0bd7f62a9b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"伊藤, 光平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"安戸, 僚汰"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kohei, Ito","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ryota, Yasudo","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Flow-in-Cloud (FiC) は複数の FPGA を高速シリアルリンクで接続したシステムで，multi-access edge computing (MEC) での計算機システムのプロトタイプとして開発が行われている．MEC での時間制約のある処理を行うために，FiC では時間をタイムスロットという単位で分割して通信路を複数の通信で共有する static time-division multiplexing (STDM) ネットワークを採用している．ただし，STDM ネットワークには通信性能がタイムスロットに制約されてしまうという欠点が存在する．タイムスロット数が大きくなってしまうと FPGA システム内での通信性能が低下してしまう．タイムスロット数はアプリケーションがどのようにマッピングされるかに大きく依存する．適切にマッピングを行うことで必要最小限のタイムスロット数でアプリケーションを実行できる．本研究では FiC でのアプリケーションマッピングの定式化とスロット数の最小化を目的としたアプリケーションマッピングツールの提案を行う．また，本提案ツールではこれまで FiC に実装されてきたマルチキャスト機能や multi-ejection STDM スイッチにも対応させた．全対全通信を行うアプリケーションにおいてはこれら 2 つの機能を用いることで，これら 2 つの機能を用いない場合の 0.32～0.41 倍のスロット数でマッピングを行うことに成功した．また，ネットワークサイズが小さいいくつかのケースでは本提案ツールを用いることで全対全通信のアプリケーションを最適なスロット数でマッピングできたことを確認した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-03-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"9","bibliographicVolumeNumber":"2022-ARC-248"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"updated":"2025-01-19T15:37:24.411421+00:00","created":"2025-01-19T01:17:36.213128+00:00","links":{}}