{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00217090","sets":["1164:1579:10818:10892"]},"path":["10892"],"owner":"44499","recid":"217090","title":["RISC-Vをベースアーキテクチャとする自動メモ化プロセッサの設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-03-03"},"_buckets":{"deposit":"c1861bf7-3d37-4103-89d5-5f70921d62e3"},"_deposit":{"id":"217090","pid":{"type":"depid","value":"217090","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"RISC-Vをベースアーキテクチャとする自動メモ化プロセッサの設計","author_link":["561701","561702","561700","561699"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"RISC-Vをベースアーキテクチャとする自動メモ化プロセッサの設計"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサ・アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-03-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"名古屋工業大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nagoya Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/217090/files/IPSJ-ARC22248002.pdf","label":"IPSJ-ARC22248002.pdf"},"date":[{"dateType":"Available","dateValue":"2024-03-03"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22248002.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"35824a22-eba7-4ffb-bbb2-aa6529b949dd","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"宮川, 晃輔"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中原, 博研"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"津邑, 公暁"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中島, 康彦"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々は計算再利用に基づいた高速化手法を採用した自動メモ化プロセッサを提案している.自動メモ化プロセッサは再利用対象である関数の実行時に,その関数の入出力を記憶する.その後,同一関数を同一入力により再実行しようとした際に,過去に記憶した出力を再利用することでその実行自体を省略する.これまで我々は,自動メモ化プロセッサのシミュレーションによる評価を行ってきた.しかし,その評価は一部の限定的なアーキテクチャでのシミュレーションにとどまっており,自動メモ化プロセッサの汎用性や実用性を十分に評価できていない可能性がある.そこで,本稿では,オープンかつ標準的な命令セットアーキテクチャとして注目を集めている RISC-V を新たに自動メモ化プロセッサのベースアーキテクチャとして採用し,その実装や評価を通じて自動メモ化プロセッサの汎用的実用性や改良の余地を検討する.RISC-V をベースアーキテクチャとする自動メモ化プロセッサを設計し,評価を行った結果,その実行サイクル数は,自動メモ化機構を実装しない場合と比較して,最大 49.0% 減少,平均 6.2% 増加となった.実行サイクル数の削減に成功した場合が存在したことから,RISC-V をベースアーキテクチャとする自動メモ化プロセッサは,既存の自動メモ化プロセッサと同様に性能向上が期待できることが確認できた.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"14","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ(ARC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-03-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"2022-ARC-248"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":217090,"updated":"2025-01-19T15:37:32.966082+00:00","links":{},"created":"2025-01-19T01:17:35.806932+00:00"}