@inproceedings{oai:ipsj.ixsq.nii.ac.jp:00216185,
 author = {Wenkang, Huang and Yanzhi, Li and Yoichi, Ishiwata and Midori, Sugaya and Wenkang, Huang and Yanzhi, Li and Yoichi, Ishiwata and Midori, Sugaya},
 book = {Proceedings of Asia Pacific Conference on Robot IoT System Development and Platform},
 month = {Jan},
 note = {Currently, FPGAs are expected to be applied to the edge computing systems as the hardware accelerators with low power consumption and high performance. Since the edge computers are close to users, they are expected to handle the privacy-related information, but the information security has not been sufficiently discussed. Therefore, in this study, we have proposed a system that integrates data responsiveness and security by encrypting the data aggregated in edge server which is based on fogcached (DRAM/NVMM), computing with a FPGA of low power consumption and high performance, and storing it in the nonvolatile memory (NVMM). By evaluating the encryption performance of FPGA, we find that it is faster and consumes less power than a processor with the same level of power consumption., Currently, FPGAs are expected to be applied to the edge computing systems as the hardware accelerators with low power consumption and high performance. Since the edge computers are close to users, they are expected to handle the privacy-related information, but the information security has not been sufficiently discussed. Therefore, in this study, we have proposed a system that integrates data responsiveness and security by encrypting the data aggregated in edge server which is based on fogcached (DRAM/NVMM), computing with a FPGA of low power consumption and high performance, and storing it in the nonvolatile memory (NVMM). By evaluating the encryption performance of FPGA, we find that it is faster and consumes less power than a processor with the same level of power consumption.},
 pages = {55--60},
 publisher = {情報処理学会},
 title = {Proposal of a Secure and Highly Reliable Edge System that Integrates DRAM/NVMM and FPGA},
 volume = {2021},
 year = {2022}
}