{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00216113","sets":["1164:1579:10818:10819"]},"path":["10819"],"owner":"44499","recid":"216113","title":["再構成可能仮想アクセラレータ(ReVA) の実現に向けたキャッシュコヒーレントな相互接続規格の検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-01-17"},"_buckets":{"deposit":"6682876f-8e36-421d-bb3a-ac08ee0b6d2e"},"_deposit":{"id":"216113","pid":{"type":"depid","value":"216113","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"再構成可能仮想アクセラレータ(ReVA) の実現に向けたキャッシュコヒーレントな相互接続規格の検討","author_link":["557507","557505","557503","557504","557508","557506"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"再構成可能仮想アクセラレータ(ReVA) の実現に向けたキャッシュコヒーレントな相互接続規格の検討"},{"subitem_title":"Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA)","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"HPC","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-01-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京農工大学工学部情報工学科"},{"subitem_text_value":" 東京農工大学大学院工学府電子情報工学専攻"},{"subitem_text_value":"東京農工大学大学院工学研究院先端情報科学部門"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer and Information Sciences, Faculty of Engineering, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronic and Information Engineering, Graduate School of Engineering, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Division of Advanced Information Technology and Computer Science, Institute of Engineering, Tokyo University of Agriculture and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/216113/files/IPSJ-ARC22247026.pdf","label":"IPSJ-ARC22247026.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22247026.pdf","filesize":[{"value":"1.9 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"3ccf3f62-4b33-4816-95a2-eb47aa3b6ddf","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"前田, 依莉子"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"照屋, 大地"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中條, 拓伯"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Eriko, Maeda","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Daichi, Teruya","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hironori, Nakajo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，HPC や AI などの演算処理において計算量やデータの大規模化が進み，そのハードウェアアクセラレーションにおいてリソース不足やアクセラレータ構成の複雑化が課題となっている．これに関連して，筆者ら は過去に再構成可能アクセラレータ ReVA (Reconfigurable Virtual Accelerator) の構想を発表したが，当時は DSM 構築のためのインターコネクトやコヒーレンス処理の実現が困難であった．これらの課題について，本稿では，キャッ シュコヒーレントなインターコネクト規格である CXL (Compute Express Link) に着目し，CXL を用いた ReVA を提案するとともに，その実現可能性を検討する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In recent years, the amount of computation and data in HPC, AI, and other computational processing has become increasingly large, and hardware acceleration has become an issue of insufficient resources and complex accelerator configurations. The authors have presented the concept of Reconfigurable Virtual Accelerator (ReVA) in the past. However, it was not easy to realize the interconnect and coherence processing for DSM implementation. In this paper, we focus on CXL (Compute Express Link), which is a cache-coherent interconnect standard. We propose ReVA again using CXL and study its feasibility.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-01-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"26","bibliographicVolumeNumber":"2022-ARC-247"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":216113,"updated":"2025-01-19T15:55:47.942181+00:00","links":{},"created":"2025-01-19T01:16:50.256556+00:00"}