{"id":216096,"updated":"2025-01-19T15:56:06.607899+00:00","links":{},"created":"2025-01-19T01:16:49.302422+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00216096","sets":["1164:1579:10818:10819"]},"path":["10819"],"owner":"44499","recid":"216096","title":["仮想エンジンアーキテクチャにおけるRISC-V 同時マルチスレッディング（SMT）コアの実現"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-01-17"},"_buckets":{"deposit":"fae4a25b-5e4d-43f7-a51e-a2aa101b5e8e"},"_deposit":{"id":"216096","pid":{"type":"depid","value":"216096","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"仮想エンジンアーキテクチャにおけるRISC-V 同時マルチスレッディング（SMT）コアの実現","author_link":["557390","557391","557389","557392","557382","557393","557388","557383","557384","557381","557387","557380","557385","557386"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"仮想エンジンアーキテクチャにおけるRISC-V 同時マルチスレッディング（SMT）コアの実現"},{"subitem_title":"Implementation of a RISC-V SMT Core in Virtual Engine Architecture","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-01-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京農工大学工学部情報工学科"},{"subitem_text_value":"東京農工大学工学部情報工学科"},{"subitem_text_value":"東京農工大学大学院工学府情報工学専攻"},{"subitem_text_value":"東京農工大学大学院工学府情報工学専攻"},{"subitem_text_value":"ArchiTek株式会社"},{"subitem_text_value":"ArchiTek株式会社"},{"subitem_text_value":"東京農工大学大学院工学研究院先端情報科学部門"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer and Information Sciences, Faculty of Engineering, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":" Department of Computer and Information Sciences, Faculty of Engineering, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Division of Advanced Information Technology and Computer Science, Graduate School of Engineering, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"Division of Advanced Information Technology and Computer Science, Graduate School of Engineering, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"ArchiTek Corporation","subitem_text_language":"en"},{"subitem_text_value":"ArchiTek Corporation","subitem_text_language":"en"},{"subitem_text_value":" Division of Advanced Information Technology and Computer Science, Institute of Engineering, Tokyo University of Agriculture and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/216096/files/IPSJ-ARC22247009.pdf","label":"IPSJ-ARC22247009.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22247009.pdf","filesize":[{"value":"1.8 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"2b82c25f-254f-434d-8bad-b56d6cdcbec2","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田中, 秀太朗"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"田中, 友章"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"長岡, 慶太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"東, 良輔"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"関部, 勉"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高田, 周一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中條, 拓伯"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hidetaro, Tanaka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tomoaki, Tanaka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Keita, Nagaoka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ryosuke, Higashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsutomu, Sekibe","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shuichi, Takada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hironori, Nakajo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"異なる目的に特化したエンジンを複数種類搭載し動作するヘテロジニアス構成の仮想エンジンアーキテクチャ上で，同時マルチスレッディング（SMT）が動作可能な RISC-V コアである CRVS コアを実装した．SMT では単にマルチコア化するよりも低リソースでの複数スレッド同時実行が可能という長所がある．また，CRVS の位置付けとしては SMT を活かした他エンジンの動作支援が挙げられる．なお，当 RISC-V コアは ArchiTek 社が開発するエッジ AI 向けチップ “Chichibu” に搭載される予定である．本研究では過去の実装と比較しリソース使用量を半分以下に削減し，またメモリに遅延がある場合でも SMT を用いることにより 3% から 6% 程度 IPC が向上した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been implemented. In the arcitecture multiple types of engines which are specialized for different purposes are conducted. As the advantage of SMT, the RISC-V SMT core allows multiple threads to be executed simultaneously at a lower cost than simply using multiple cores. The RISC-V core supports operations of other engines under the SMT mechanism in order to be installed in ”Chichibu” which is developed by ArchiTek as a multicore chip for edge AI. In this implementation, we have reduced the hardware resource usage to less than half of the previous implementation. Also the IPC has been improved by about 3% to 6% by using SMT even when delays in instruction and data memory is brought.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-01-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"9","bibliographicVolumeNumber":"2022-ARC-247"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}