{"created":"2025-01-19T01:16:48.910449+00:00","updated":"2025-01-19T15:56:14.461223+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00216089","sets":["1164:1579:10818:10819"]},"path":["10819"],"owner":"44499","recid":"216089","title":["SD数を用いた法集合{2????, 2???? + 1, 2???? − 1}の剰余数系逆変換回路の研究"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-01-17"},"_buckets":{"deposit":"303fc584-9948-4d87-b613-6131b80c13f1"},"_deposit":{"id":"216089","pid":{"type":"depid","value":"216089","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"SD数を用いた法集合{2????, 2???? + 1, 2???? − 1}の剰余数系逆変換回路の研究","author_link":["557355","557354","557356","557359","557357","557358"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"SD数を用いた法集合{2????, 2???? + 1, 2???? − 1}の剰余数系逆変換回路の研究"},{"subitem_title":"Study on Reverse Converters for RNS moduli set {2????, 2???? + 1, 2???? − 1} using Signed-Digit numbers","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路設計 ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-01-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"群馬大学大学院理工学府理工学専攻"},{"subitem_text_value":"群馬大学大学院理工学府理工学専攻"},{"subitem_text_value":"群馬大学大学院理工学府理工学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Gunma University","subitem_text_language":"en"},{"subitem_text_value":" Graduate School of Science and Technology, Gunma University","subitem_text_language":"en"},{"subitem_text_value":" Graduate School of Science and Technology, Gunma University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/216089/files/IPSJ-ARC22247002.pdf","label":"IPSJ-ARC22247002.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC22247002.pdf","filesize":[{"value":"1.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"e8f5cd16-e307-4fad-8c66-6f57bc051e95","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"森井, 貴大"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"田中, 勇樹"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"魏, 書剛"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takahiro, Morii","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuuki, Tanaka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shugang, Wei","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では，法集合 {2???? , 2???? + 1, 2???? − 1} の剰余数系において，剰余数を重み数へ変換する逆変換回路を提案する．逆変換には SD 数（Signed-Digit 数），SD 数加算アルゴリズムを適用することにより逆変換処理の剰余加算回数を減らし，桁数への依存度の低い逆変換回路を設計した．また，負の値を取ることがある剰余 SD 数の符号判別及び符号補正をより高速に行うため，SD 数-二進数減算アルゴリズムを利用した新たなアルゴリズムを提案する．加えて提案アルゴリズムをハードウェア記述言語を用いて回路実装し，0.18µm CMOS ゲートアレイ設計ライブラリを用いて評価を行った．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this study, we propose reverse converters for moduli set {2???? , 2???? + 1, 2???? − 1} that convert residue number system to weighted number system. By using SD(Signed-Digit) number and SD number addition algorithm, we can reduce number of modular addition of reverse conversion. Moreover, we consider a method that can detect a number is represented by a negative value and obtain an equivalent positive value of the residue SD number that may take negative values at a higher speed by using SD-binary subtraction algorithm. We have designed the reverse conversion circuit with a hardware description language by using a 0.18µm CMOS gate array technology library.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-01-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"2022-ARC-247"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":216089,"links":{}}