{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00216060","sets":["1164:2036:10820:10821"]},"path":["10821"],"owner":"44499","recid":"216060","title":["RTOS利用システムの汎用高位合成系を用いたフルハードウェア化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2022-01-17"},"_buckets":{"deposit":"cfa6a6f4-6549-4ccb-8742-9b65e3dc34f1"},"_deposit":{"id":"216060","pid":{"type":"depid","value":"216060","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"RTOS利用システムの汎用高位合成系を用いたフルハードウェア化","author_link":["557190","557189","557194","557195","557191","557196","557193","557192","557187","557188"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"RTOS利用システムの汎用高位合成系を用いたフルハードウェア化"},{"subitem_title":"Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路設計 ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2022-01-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"関西学院大学"},{"subitem_text_value":"関西学院大学"},{"subitem_text_value":"関西学院大学"},{"subitem_text_value":"立命館大学"},{"subitem_text_value":"京都高度技術研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kwansei Gakuin University","subitem_text_language":"en"},{"subitem_text_value":"Kwansei Gakuin University","subitem_text_language":"en"},{"subitem_text_value":"Kwansei Gakuin University","subitem_text_language":"en"},{"subitem_text_value":"Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"ASTEM RI KYOTO","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/216060/files/IPSJ-SLDM22197003.pdf","label":"IPSJ-SLDM22197003.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM22197003.pdf","filesize":[{"value":"1.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"542f8404-420c-407f-9a84-b16e007e4cf0","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2022 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"安堂, 拓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"石井, 雄吾"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"石浦, 菜岐佐"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"冨山, 宏之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"神原, 弘之"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takuya, Ando","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yugo, Ishii","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nagisa, Ishiura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroyuki, Tomiyama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroyuki, Kanbara","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，RTOS を用いたシステムのフルハードウェア実装を汎用的な高位合成システムによって行う手法を提案する．六車らは，タスク/ハンドラおよび RTOS のカーネル機能を全てハードウェア化することによりリアルタイムシステムの応答性能を飛躍的に向上させる手法を提案しているが，独自のバイナリ合成システムに依存しており，汎用的な高位合成システムではタスクの実行制御や共有変数へのアクセスをそのまま合成することが困難であった．本稿では，タスクの実行を実行/停止信号ではなく，タスクからのサービス要求の実行/保留により制御する方式と，メモリアクセスのラッパークラスを定義して最小限の書き換えで共有変数へのアクセスを可能にする方法により，一般的な高位合成システムで RTOS 利用システムのフルハードウェア実装を可能にする．本手法を TOPPERS/ASP3 カーネル付属サンプル “sample1” を縮小したプログラムに適用した結果，Xilinx Vitis HLS を用いてハードウェアを合成することができた．また，これにより従来手法に比べて回路規模を大幅に削減することができた．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level synthesizer. Muguruma has proposed a scheme where both all the tasks/handlers and all the RTOS functions are implemented as hardware. However, it assumes the use of a dedicated binary synthesizer, ACAP, where generated task modules have stall ports for suspending their execution and accesses to globally shared variables are realized as loads/stores using automatically generated addresses, which are not necessarily possible by general high-level synthesizers. This paper proposes a method where execution of tasks is controlled by allowing/disabling execution of service calls from the tasks, and code transformation using a wrapper class for shared variable accesses and functions within a function, to make general high-level synthesizers applicable to the full-hardware scheme. Based on the proposed methods, a hardware module for a reduced version of “sample1” bundled with TOPPERS/ASP has been successfully implemented as hardware using Xilinx Vitis HLS, where the size of the resulting circuit was substantially smaller than that by the previous method.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2022-01-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"2022-SLDM-197"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":216060,"updated":"2025-01-19T15:56:44.647342+00:00","links":{},"created":"2025-01-19T01:16:47.293438+00:00"}