{"created":"2025-01-19T01:15:27.420590+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00214651","sets":["6504:10735:10736"]},"path":["10736"],"owner":"44499","recid":"214651","title":["FPGAを用いたFFT処理ROSノードの初期評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-03-04"},"_buckets":{"deposit":"dac09164-6316-411d-8b42-91f9565d634e"},"_deposit":{"id":"214651","pid":{"type":"depid","value":"214651","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGAを用いたFFT処理ROSノードの初期評価","author_link":["551817","551818","551819","551816","551820"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAを用いたFFT処理ROSノードの初期評価"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"コンピュータシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"22","publish_date":"2021-03-04","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東海大"},{"subitem_text_value":"トロント大"},{"subitem_text_value":"東海大"},{"subitem_text_value":"東海大"},{"subitem_text_value":"東海大"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/214651/files/IPSJ-Z83-6H-02.pdf","label":"IPSJ-Z83-6H-02.pdf"},"date":[{"dateType":"Available","dateValue":"2021-12-28"}],"format":"application/pdf","filename":"IPSJ-Z83-6H-02.pdf","filesize":[{"value":"408.8 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"68116f62-6ccf-4402-8bb3-e0afaa45430b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Information Processing Society of Japan"}]},"item_22_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"星野, 美如"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Daniel, Pinheiro Leal"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"渡辺, 晴美"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐藤, 未来子"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"大川, 猛"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FFT処理をFPGA上で低遅延に行うシステムをROSノード化することで容易な応用を可能し、ロボットシステム開発に貢献する。ロボットシステム開発では、制御のために用いられるデータ解析処理の低遅延化が求められている。複雑な制御を可能とするためには膨大なデータを扱う必要があるが、データ量の増加に伴い計算処理時間も増加してしまう問題がある。これを解決する為、FFTにFPGAを用いることで低遅延な処理を行い、さらにノードとして実現することで汎用化する。本研究ではFPGAをROSノード化し、低遅延なFFT処理をロボットシステムに容易に組み込むことができる環境を提案する。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"80","bibliographic_titles":[{"bibliographic_title":"第83回全国大会講演論文集"}],"bibliographicPageStart":"79","bibliographicIssueDates":{"bibliographicIssueDate":"2021-03-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2021"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"links":{},"id":214651,"updated":"2025-01-19T16:31:56.806951+00:00"}