{"created":"2025-01-19T01:14:52.350779+00:00","updated":"2025-01-19T16:55:42.676292+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00214035","sets":["1164:2036:10484:10753"]},"path":["10753"],"owner":"44499","recid":"214035","title":["マルチFPGAシステム上への,動的な通信優先度変化を実現するハイブリッドルータの実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-11-24"},"_buckets":{"deposit":"c2ff64a8-73d4-469d-84fa-3962ee719302"},"_deposit":{"id":"214035","pid":{"type":"depid","value":"214035","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"マルチFPGAシステム上への,動的な通信優先度変化を実現するハイブリッドルータの実装","author_link":["548375","548374","548366","548371","548368","548367","548373","548372","548369","548370"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチFPGAシステム上への,動的な通信優先度変化を実現するハイブリッドルータの実装"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"応用事例","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-11-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing 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光平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯塚, 健介"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"弘中, 和衛"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tomoki, Shimizu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kohei, Ito","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kensuke, Iizuka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazuei, Hironaka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"現在我々が開発しているマルチ FPGA システム,Flow-in-Cloud (FiC) システムは複数の中規模な FPGA を高速シリアルリンクで直接相互接続し,省電力と高演算性能を両立する.この FiC システムは,無線網基地局上に設置されたサーバにエッジデバイスの演算をオフロードする Multi-Access Edge Computing (MEC) への利用が期待されている.MEC におけるタイミングクリティカルなジョブに対応するため,FiC では遅延とバンド幅が予測可能な Static Time Division Multiplexing (STDM) 方式を FPGA 間の結合網に用いているが,この方式は各リンクの利用率が低下し,通信レイテンシが大きくなるという問題が存在する.これを解決するため,低優先度のパケットスイッチ方式と高優先度の STDM 方式を併用するハイブリッドルータを各 FPGA 上に実装することで,タイミングクリティカルなジョブの通信 QoS を保証しつつ各リンクをベストエフォートに使用できる.しかし,パケットスイッチ方式によるネットワーク利用が十分でない限り STDM を割り当てられたタイミングクリティカルなジョブは依然としてリンクを十分に利用できない.本研究では,ハイブリッドルータのバッファ使用量を指標としてネットワーク負荷を監視し,タイミングクリティカルなジョブの通信方式を動的に切り替えるアルゴリズムを提案する.この手法を用いることで,タイミングクリティカルなジョブはネットワーク負荷が高い場合は高い通信優先度により QoS を保証するSTDM 方式を利用し,ネットワーク負荷が低い場合はベストエフォートなパケットスイッチ方式を利用することが可能となる.評価は 24 台からなる実機 FPGA クラスタ上で行われ,特に実アプリケーションである CG 法においてネットワーク負荷を様々に変化させた場合,動的な切り替え手法は特に輻輳時,パケットスイッチ方式に対し実行時間を 24.6% 高速化した.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術(SLDM)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-11-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"25","bibliographicVolumeNumber":"2021-SLDM-196"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":214035,"links":{}}