{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00214033","sets":["1164:2036:10484:10753"]},"path":["10753"],"owner":"44499","recid":"214033","title":["正確丸めを実現するFPGA向き指数関数計算法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-11-24"},"_buckets":{"deposit":"e954c695-e49b-4990-8dc8-cffe911e4475"},"_deposit":{"id":"214033","pid":{"type":"depid","value":"214033","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"正確丸めを実現するFPGA向き指数関数計算法","author_link":["548362","548363","548364","548365"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"正確丸めを実現するFPGA向き指数関数計算法"},{"subitem_title":"Calculation method of correctly rounded exponential function on an FPGA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"VLSI設計技術とアルゴリズム","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-11-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学情報学研究科"},{"subitem_text_value":"京都大学情報学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/214033/files/IPSJ-SLDM21196024.pdf","label":"IPSJ-SLDM21196024.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM21196024.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"cce48a5c-3f9b-4fda-96f2-01facaa614eb","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"原口, 卓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高木, 直史"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takuya, Haraguchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Naofumi, Takagi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"IEEE754 で正確に丸めることが推奨されている関数の一つ，指数関数 exp の正確丸めを実現する FPGA 向きの計算法を提案する．本計算法では，高基数 STL 法とテイラー展開による近似を用いて exp の計算を行う．入力の正負に応じて計算誤差の生じる方向を一方向に制限することにより，正確丸めに必要な精度を 158 ビットから 114 ビットに低減している．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We propose the FPGA-oriented calculation method of correctly rounded exponential function, exp, which is one of the functions recommended for correct rounding in IEEE754 standard. In this calculation method, exp is calculated with high-radix STL method and Taylor series approximation. By restricting the direction of the calculation error to one direction depending on the sign of the input, we reduce the accuracy required for correct rounding from 158 bits to 114 bits.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-11-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"24","bibliographicVolumeNumber":"2021-SLDM-196"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":214033,"updated":"2025-01-19T16:55:44.994452+00:00","links":{},"created":"2025-01-19T01:14:52.236526+00:00"}