{"created":"2025-01-19T01:14:51.425362+00:00","updated":"2025-01-19T16:56:00.547263+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00214019","sets":["1164:2036:10484:10753"]},"path":["10753"],"owner":"44499","recid":"214019","title":["SRAMの動作電圧引き下げによるニューラルネットワークの低電力化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-11-24"},"_buckets":{"deposit":"caabd2e9-98ec-4a96-a7db-3d5012405c56"},"_deposit":{"id":"214019","pid":{"type":"depid","value":"214019","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"SRAMの動作電圧引き下げによるニューラルネットワークの低電力化","author_link":["548288","548287","548290","548289"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"SRAMの動作電圧引き下げによるニューラルネットワークの低電力化"},{"subitem_title":"Low power neural network by reducing the operating voltage of SRAM","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"低消費電力及びモデル検証","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-11-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"千葉大学大学院融合理工学府"},{"subitem_text_value":"千葉大学大学院工学研究院"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Engineering, Chiba University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Chiba University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/214019/files/IPSJ-SLDM21196010.pdf","label":"IPSJ-SLDM21196010.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM21196010.pdf","filesize":[{"value":"2.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"131ea494-4f2e-42d6-905d-aa98cf0fad58","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"高津, 啓佑"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"難波, 一輝"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Keisuke, Kozu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazuteru, Namba","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"機械学習の技術の進歩に伴い，ネットワークが複雑化し計算量が増加している．それに伴い，学習のプロセスにかかる計算時間や消費電力の増加が問題となっている．この問題を解決するためのアプローチとして，ニューラルネットワークのエラー耐性に注目が集まっている．ニューラルネットワークは多少の誤差を許容できるため，精度を犠牲に計算速度や消費電力の削減を行うことができる．そこで， 本論文では重みの保存に使用される SRAM の動作電圧を引き下げることで，回路全体の消費電力を削減する手法を提案する．一般に SRAM  は動作電圧を引き下げることで，ビット誤り率 (BER) が増加する．BER と認識率の関係を調査し，高い認識率を保ちながら消費電力を引き下げることのできる回路モデルを示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"With the advancement of machine learning technology, networks are becoming more and more complex and computationally intensive. As a result, the computation time and power  consumption for the learning process are increasing. As an approach to solving this problem, the error tolerance of neural networks has been attracting attention. Since neural networks can tolerate small error s, it is possible to reduce the computation speed and power consumption at the expense of accuracy. In this paper, we proposed a method to reduce the power consumption of the entire circuit by lowering the operating voltage of the SRAM that stores the weights. We also investigated the relationship between BER and recognition rate, and showed a circuit model that can reduce the power consumption while maintaining a high recognition rate. ","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"5","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-11-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"10","bibliographicVolumeNumber":"2021-SLDM-196"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":214019,"links":{}}