{"created":"2025-01-19T01:14:51.188662+00:00","updated":"2025-01-19T16:56:05.258660+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00214015","sets":["1164:2036:10484:10753"]},"path":["10753"],"owner":"44499","recid":"214015","title":["Sparsity-Gradient を用いた深層学習モデルの圧縮とVitis-AI への実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-11-24"},"_buckets":{"deposit":"67b77b9d-f483-40f2-a825-14c2b0138aa8"},"_deposit":{"id":"214015","pid":{"type":"depid","value":"214015","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Sparsity-Gradient を用いた深層学習モデルの圧縮とVitis-AI への実装","author_link":["548262","548261","548263","548259","548264","548260"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Sparsity-Gradient を用いた深層学習モデルの圧縮とVitis-AI への実装"},{"subitem_title":"Sparsity-Gradient-Based Pruning and the Vitis-AI Implementation for Compacting Deep Learning","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"機械学習","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2021-11-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"立命館大学理工学部電子情報工学科"},{"subitem_text_value":"立命館大学理工学部電子情報工学科"},{"subitem_text_value":"立命館大学理工学部電子情報工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Electronic and Computer Engineering, College of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronic and Computer Engineering, College of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronic and Computer Engineering, College of Science and Engineering, Ritsumeikan University,","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/214015/files/IPSJ-SLDM21196006.pdf","label":"IPSJ-SLDM21196006.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM21196006.pdf","filesize":[{"value":"2.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"ad0c33f1-36ac-405c-a220-20fba5953a7b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2021 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"李, 恒毅"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"岳, 学彬"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"孟, 林"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hengyi, Li","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Xuebin, Yue","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Lin, Meng","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"The paper proposes a Sparsity-Gradient-Based layer-wise Pruning technique for compacting deep neural networks and accelerates the network by the Vitis AI on the Xilinx FPGA platform. The experimental results show that nearly 99.67% of parameters and 97.91% floating-point operations are pruned with only 1.2% accuracy decreased. With the support of Vitis AI, which offers a solution for adaptable and real-time AI inference acceleration, the pruned model is quantized and implemented on FPGA. The inference process achieves the throughput of 237.80 floating-point operations per second and running time of 4.21ms concerning VGG13BN, about 10 × speedup compared with the original model at single-thread mode. The paper also makes an in-depth analysis of the efficiency and utilization of the inference implementation, including the layer-wise workloads, running time, memory consumption, and so on. With the comprehensive analysis of the model deployed on FPGA, we plan to make further efforts to design the acceleration engine on hardware level by utilizing the potential of FPGA.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The paper proposes a Sparsity-Gradient-Based layer-wise Pruning technique for compacting deep neural networks and accelerates the network by the Vitis AI on the Xilinx FPGA platform. The experimental results show that nearly 99.67% of parameters and 97.91% floating-point operations are pruned with only 1.2% accuracy decreased. With the support of Vitis AI, which offers a solution for adaptable and real-time AI inference acceleration, the pruned model is quantized and implemented on FPGA. The inference process achieves the throughput of 237.80 floating-point operations per second and running time of 4.21ms concerning VGG13BN, about 10 × speedup compared with the original model at single-thread mode. The paper also makes an in-depth analysis of the efficiency and utilization of the inference implementation, including the layer-wise workloads, running time, memory consumption, and so on. With the comprehensive analysis of the model deployed on FPGA, we plan to make further efforts to design the acceleration engine on hardware level by utilizing the potential of FPGA.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2021-11-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"6","bibliographicVolumeNumber":"2021-SLDM-196"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":214015,"links":{}}